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21 条记录 (耗时 0.018 秒)

    Reduced susceptibility to electrostatic discharge during 3D semiconductor device bonding and assembly
    4.
    发明授权
    Reduced susceptibility to electrostatic discharge during 3D semiconductor device bonding and assembly 有权
    在3D半导体器件接合和​​组装期间降低对静电放电的敏感性

    公开(公告)号：US08198736B2

    公开(公告)日：2012-06-12

    申请号：US12421096

    申请日：2009-04-09

    申请人： Brian M. Henderson ,  Reza Jalilizeinali ,  Shiqun Gu

    发明人： Brian M. Henderson ,  Reza Jalilizeinali ,  Shiqun Gu

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L23/488 ,  H01L21/50 ,  H01L21/67092 ,  H01L23/60 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16 ,  H01L2225/06513

    摘要： A method to reduce electrostatic discharge susceptibility when assembling a stacked IC device. The method includes coupling a ground plane of a first semiconductor device and a ground plane of a second semiconductor device to substantially a same electrical potential. Active circuitry on the first semiconductor device and active circuitry on the second semiconductor device are electrically coupled after the ground planes are coupled. Electrically coupling the ground planes of the first and the second semiconductor device creates a preferred electrostatic discharge path to ground, thus minimizing potential damage to sensitive circuit elements.

    摘要翻译： 一种组装堆叠IC器件时降低静电放电敏感性的方法。 该方法包括将第一半导体器件的接地平面和第二半导体器件的接地平面耦合到基本上相同的电位。 第一半导体器件上的有源电路和第二半导体器件上的有源电路在接地平面耦合之后被电耦合。 电耦合第一和第二半导体器件的接地平面产生优选的接地静电放电路径，从而最小化对敏感电路元件的潜在损害。

    Reduced Susceptibility To Electrostatic Discharge During 3D Semiconductor Device Bonding and Assembly
    6.
    发明申请
    Reduced Susceptibility To Electrostatic Discharge During 3D Semiconductor Device Bonding and Assembly 有权
    降低3D半导体器件粘合和组装过程中静电放电的敏感性

    公开(公告)号：US20100258949A1

    公开(公告)日：2010-10-14

    申请号：US12421096

    申请日：2009-04-09

    申请人： Brian M. Henderson ,  Reza Jalilizeinali ,  Shiqun Gu

    发明人： Brian M. Henderson ,  Reza Jalilizeinali ,  Shiqun Gu

    IPC分类号： H01L23/52 ,  H01L21/50 ,  H05K3/36 ,  H05K13/00

    CPC分类号： H01L23/488 ,  H01L21/50 ,  H01L21/67092 ,  H01L23/60 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16 ,  H01L2225/06513

    摘要： A method to reduce electrostatic discharge susceptibility when assembling a stacked IC device. The method includes coupling a ground plane of a first semiconductor device and a ground plane of a second semiconductor device to substantially a same electrical potential. Active circuitry on the first semiconductor device and active circuitry on the second semiconductor device are electrically coupled after the ground planes are coupled. Electrically coupling the ground planes of the first and the second semiconductor device creates a preferred electrostatic discharge path to ground, thus minimizing potential damage to sensitive circuit elements.

    摘要翻译： 一种组装堆叠IC器件时降低静电放电敏感性的方法。 该方法包括将第一半导体器件的接地平面和第二半导体器件的接地平面耦合到基本上相同的电位。 第一半导体器件上的有源电路和第二半导体器件上的有源电路在接地平面耦合之后被电耦合。 电耦合第一和第二半导体器件的接地平面产生优选的接地静电放电路径，从而最小化对敏感电路元件的潜在损害。

    Active Diode Having No Gate and No Shallow Trench Isolation
    9.
    发明申请
    Active Diode Having No Gate and No Shallow Trench Isolation 有权
    没有门的活性二极管和没有浅沟槽隔离

    公开(公告)号：US20110084362A1

    公开(公告)日：2011-04-14

    申请号：US12751903

    申请日：2010-03-31

    申请人： Reza Jalilizeinali ,  Eugene R. Worley ,  Evan Siansuri ,  Sreeker R. Dundigal

    发明人： Reza Jalilizeinali ,  Eugene R. Worley ,  Evan Siansuri ,  Sreeker R. Dundigal

    IPC分类号： H01L29/861 ,  H01L21/762

    CPC分类号： H01L29/8611 ,  H01L29/0692 ,  H01L29/66128

    摘要： An active diode with fast turn-on time, low capacitance, and low turn-on resistance may be manufactured without a gate and without a shallow trench isolation region between doped regions of the diode. A short conduction path in the active diode allows a fast turn-on time, and a lack of gate oxide reduces susceptibility of the active diode to extreme voltages. The active diode may be implemented in integrated circuits to prevent and reduce damage from electrostatic discharge (ESD) events. Manufacturing the active diode is accomplished by depositing a salicide block between doped regions of the diode before salicidation. After the salicide layers are formed on the doped regions, the salicide block is removed.

    摘要翻译： 可以在没有栅极并且在二极管的掺杂区域之间没有浅沟槽隔离区域的情况下制造具有快导通时间，低电容和低导通电阻的有源二极管。 有源二极管中的短导通路径允许快速导通时间，并且缺少栅极氧化物降低有源二极管对极端电压的敏感性。 有源二极管可以在集成电路中实现，以防止和减少静电放电（ESD）事件的损坏。 有源二极管的制造是通过在盐析之前在二极管的掺杂区域之间沉积自对准硅化物块来实现的。 在掺杂区域上形成自对准硅化物层之后，去除硅化物块。

    Active diode having no gate and no shallow trench isolation
    10.
    发明授权
    Active diode having no gate and no shallow trench isolation 有权
    有源二极管没有栅极，没有浅沟槽隔离

    公开(公告)号：US09368648B2

    公开(公告)日：2016-06-14

    申请号：US12751903

    申请日：2010-03-31

    申请人： Reza Jalilizeinali ,  Eugene R. Worley ,  Evan Siansuri ,  Sreeker R. Dundigal

    发明人： Reza Jalilizeinali ,  Eugene R. Worley ,  Evan Siansuri ,  Sreeker R. Dundigal

    IPC分类号： H01L27/02 ,  H01L29/861 ,  H01L29/66 ,  H01L29/06

    CPC分类号： H01L29/8611 ,  H01L29/0692 ,  H01L29/66128

    摘要： An active diode with fast turn-on time, low capacitance, and low turn-on resistance may be manufactured without a gate and without a shallow trench isolation region between doped regions of the diode. A short conduction path in the active diode allows a fast turn-on time, and a lack of gate oxide reduces susceptibility of the active diode to extreme voltages. The active diode may be implemented in integrated circuits to prevent and reduce damage from electrostatic discharge (ESD) events. Manufacturing the active diode is accomplished by depositing a salicide block between doped regions of the diode before salicidation. After the salicide layers are formed on the doped regions, the salicide block is removed.

    摘要翻译： 可以在没有栅极并且在二极管的掺杂区域之间没有浅沟槽隔离区域的情况下制造具有快导通时间，低电容和低导通电阻的有源二极管。 有源二极管中的短导通路径允许快速导通时间，并且缺少栅极氧化物降低有源二极管对极端电压的敏感性。 有源二极管可以在集成电路中实现，以防止和减少静电放电（ESD）事件的损坏。 有源二极管的制造是通过在盐析之前在二极管的掺杂区域之间沉积自对准硅化物块来实现的。 在掺杂区域上形成自对准硅化物层之后，去除硅化物块。