公开(公告)号：US6038164A

公开(公告)日：2000-03-14

申请号：US200071

申请日：1998-11-25

申请人： Thomas Schulz ,  Thomas Aeugle ,  Wolfgang Rosner ,  Lothar Risch

发明人： Thomas Schulz ,  Thomas Aeugle ,  Wolfgang Rosner ,  Lothar Risch

IPC分类号： H01L21/8244 ,  H01L27/11 ,  G11C11/00

CPC分类号： H01L27/11 ,  H01L27/1104

摘要： The SRAM cell configuration has at least six transistors in each memory cell. Four of the transistors form a flip-flop and they are arranged at the corners of a quadrilateral. The flip-flop is driven by two of the transistors, which are disposed so as to adjoin diagonally opposite corners of the quadrilateral and outside the quadrilateral. Adjacent memory cells along a word line can be arranged in such a way that a first bit line and a second bit line of the adjacent memory cells coincide. The transistors are preferably vertical and are arranged at semiconductor structures (St1, St2, St3, St4, St5, St6) produced from a layer sequence. Two of the transistors having n-doped channel regions are preferably formed in each case on two semiconductor structures.

摘要翻译： SRAM单元配置在每个存储单元中具有至少六个晶体管。 四个晶体管形成触发器，并且它们被布置在四边形的角部。 触发器由两个晶体管驱动，这些晶体管被设置为邻接四边形的对角线相对的角部并且在四边形之外。 沿着字线的相邻存储器单元可以以相邻存储器单元的第一位线和第二位线重合的方式布置。 晶体管优选是垂直的，并且被布置在从层序列产生的半导体结构（St1，St2，St3，St4，St5，St6）处。 在每种情况下，优选在两个半导体结构上形成具有n掺杂沟道区的两个晶体管。

公开(公告)号：US6060911A

公开(公告)日：2000-05-09

申请号：US138160

申请日：1998-08-21

申请人： Thomas Schulz ,  Thomas Aeugle ,  Wolfgang Roesner ,  Lothar Risch

发明人： Thomas Schulz ,  Thomas Aeugle ,  Wolfgang Roesner ,  Lothar Risch

IPC分类号： G11C16/04 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H03K19/094 ,  H01L29/76

CPC分类号： H01L27/092 ,  H01L21/823885

摘要： In the circuit arrangement two of the four vertical transistors are complementary to the remaining two transistors. Two of the transistors are respectively arranged at the same level. For this purpose, layer structures (St1, St2, St3, St4) are structured that respectively have at least a channel layer and a source/drain region of one of the transistors. All the layer structures (St1, St2, St3, St4) can be produced from a layer sequence with only four layers. In order to avoid leakage currents due to a parasitic bipolar transistor, the layer structures (St1, St2, St3, St4) can be realized very thinly, using spacer-type masks. Electrical connections between parts of the four transistors can take place via layers of the layer sequence. The contacting to the output voltage terminal can take place via a step that is formed by two layers of the layer sequence.

摘要翻译： 在电路布置中，四个垂直晶体管中的两个与剩余的两个晶体管互补。 两个晶体管分别布置在相同的电平上。 为此，层结构（St1，St2，St3，St4）被构造成分别具有至少一个晶体管的沟道层和源极/漏极区域。 所有的层结构（St1，St2，St3，St4）可以仅由四层制成。 为了避免由寄生双极型晶体管引起的漏电流，使用间隔型掩模，可以非常薄地实现层结构（St1，St2，St3，St4）。 四个晶体管的部分之间的电连接可以通过层序列的层进行。 与输出电压端子的接触可以通过由层序列的两层形成的步骤进行。

公开(公告)号：US06459123B1

公开(公告)日：2002-10-01

申请号：US09302768

申请日：1999-04-30

申请人： Gerhard Enders ,  Thomas Schulz ,  Dietrich Widmann ,  Lothar Risch

发明人： Gerhard Enders ,  Thomas Schulz ,  Dietrich Widmann ,  Lothar Risch

IPC分类号： H01L2994

CPC分类号： H01L27/11 ,  H01L21/823885 ,  H01L27/092 ,  H01L27/1104 ,  H01L27/1203

摘要： A semiconductor body having a pair of vertical, double-gated CMOS transistors. An insulating layer extending horizontally beneath the surface of the semiconductor body such insulating layer being disposed beneath the pair of transistors. The transistors, together with additional such transistors, are arranged to form a Synchronous Dynamic Random Access Memory (SRAM) array. The array includes a plurality of SRAM cells arranged in rows and columns, each one of the cells having a WORDLINE connected to a WORLDINE CONTACT. The WORDLINE CONTACT is common to four contiguous one of the cells. One of the cells having a plurality of electrically interconnected MOS transistors arranged to provide an SRAM circuit. Each one of the cells has a VDD CONTACT and a VSS CONTACT. One of such CONTACTs is disposed centrally within each one of the cells and the other one of the CONTACTs being common to four contiguous ones of the cells. Each one of the cells has the common one of the CONTACTs and the WORDLINE CONTACT disposed at peripheral, corner regions of the cell.

摘要翻译： 具有一对垂直双门控CMOS晶体管的半导体本体。 在半导体本体的表面下水平延伸的绝缘层，该绝缘层设置在该对晶体管的下方。 晶体管与附加的这种晶体管一起被布置成形成同步动态随机存取存储器（SRAM）阵列。 阵列包括以行和列排列的多个SRAM单元，每个单元都具有连接到WORLDINE CONTACT的WORDLINE。 WORDLINE CONTACT是四个连续的一个单元格共同的。 具有多个电互连的MOS晶体管的单元之一被布置成提供SRAM电路。 每个单元都有一个VDD CONTACT和一个VSS CONTACT。 这种CONTACT之一被布置在每个单元格的中心并且另一个CONTACT被四个相邻的单元共同。 每个单元格具有共同的一个CONTACT和WORDLINE CONTACT放置在单元的外围角区域。

公开(公告)号：US06864129B2

公开(公告)日：2005-03-08

申请号：US09996279

申请日：2001-11-28

申请人： Lothar Risch ,  Wolfgang Rösner ,  Thomas Schulz

发明人： Lothar Risch ,  Wolfgang Rösner ,  Thomas Schulz

IPC分类号： H01L29/417 ,  H01L21/20 ,  H01L21/336 ,  H01L29/786 ,  H01L21/00 ,  H01L27/01

CPC分类号： H01L29/66772 ,  H01L29/78648

摘要： A double gate MOSFET transistor and a method for fabricating it are described. In this case, a semiconductor layer structure of a transistor channel to be formed is embedded in a spacer material and contact-connected by source and drain regions which are filled into depressions that are etched on opposite sides of the semiconductor layer structure. Afterwards, the spacer material is etched out selectively and replaced by the electrically conductive gate electrode material.

摘要翻译： 描述双栅极MOSFET晶体管及其制造方法。 在这种情况下，要形成的晶体管沟道的半导体层结构被嵌入到间隔物材料中，并且被源极和漏极区域接触，其被填充到在半导体层结构的相对侧被蚀刻的凹陷中。 之后，间隔材料被选择性蚀刻掉，并由导电栅电极材料代替。

公开(公告)号：US06362502B1

公开(公告)日：2002-03-26

申请号：US09692118

申请日：2000-10-19

申请人： Wolfgang Rösner ,  Thomas Schulz ,  Lothar Risch ,  Franz Hofmann

发明人： Wolfgang Rösner ,  Thomas Schulz ,  Lothar Risch ,  Franz Hofmann

IPC分类号： H01L27108

CPC分类号： H01L27/1203 ,  H01L27/108 ,  H01L27/10876

摘要： A memory cell contains a memory transistor and a transfer transistor. A gate electrode of the transfer transistor and a control gate electrode of the memory transistor are connected to a word line. The memory transistor has a floating gate electrode that is isolated from a channel region of the memory transistor by a first dielectric layer and is connected to a first source/drain region of the transfer transistor. The control gate electrode is isolated from the floating gate electrode by a second dielectric layer. A first source/drain region of the memory transistor is connected to a bit line. The memory and transfer transistors are preferably of different conductivity types. During the writing of information, the transfer transistor is in the on-state and the memory transistor is in the off-state. During the reading-out of information, the transfer transistor is in the off-state and the memory transistor is in the on-state.

摘要翻译： 存储单元包含存储晶体管和转移晶体管。 转移晶体管的栅电极和存储晶体管的控制栅电极连接到字线。 存储晶体管具有通过第一介电层与存储晶体管的沟道区隔离并与转移晶体管的第一源极/漏极区连接的浮栅电极。 控制栅电极通过第二电介质层与浮置栅电极隔离。 存储晶体管的第一源/漏区连接到位线。 存储器和转移晶体管优选地具有不同的导电类型。 在写入信息期间，传输晶体管处于导通状态，并且存储晶体管处于截止状态。 在读出信息期间，传输晶体管处于截止状态，并且存储晶体管处于导通状态。

公开(公告)号：US06337247B1

公开(公告)日：2002-01-08

申请号：US09487411

申请日：2000-01-18

申请人： Thomas Schulz ,  Thomas Äugle ,  Wolfgang Rösner ,  Lothar Risch

发明人： Thomas Schulz ,  Thomas Äugle ,  Wolfgang Rösner ,  Lothar Risch

IPC分类号： H01L21336

CPC分类号： H01L29/66666 ,  H01L29/7827 ,  H01L29/7834

摘要： A spacer is used as a mask in an etching step during which a layer structure is produced for a channel layer and for a first source/drain region. After the layer structure has been produced, the first source/drain region and a second source/drain region can be produced by implantation. The second source/drain region is self-aligned on two mutually opposite flanks of the layer structure. A gate electrode can be produced in the form of a spacer on the two flanks. In order to avoid a capacitance formed by a first contact of the gate electrode and the first source/drain region, a part of the first source/drain region may be removed. If the layer structure is produced along edges of an inner area, then a third contact of the second source/drain region may be produced inside the inner area in order to reduce the surface area of the transistor.

摘要翻译： 在蚀刻步骤中使用间隔物作为掩模，在该步骤中，为沟道层和第一源极/漏极区域产生层结构。 在生成层结构之后，可以通过注入产生第一源极/漏极区域和第二源极/漏极区域。 第二源极/漏极区域在层结构的两个相互相对的侧面上自对准。 可以在两个侧面上以间隔物的形式制造栅电极。 为了避免由栅极电极和第一源极/漏极区域的第一接触形成的电容，可以去除第一源极/漏极区域的一部分。 如果沿着内部区域的边缘产生层结构，则可以在内部区域内产生第二源极/漏极区域的第三接触，以便减小晶体管的表面积。

公开(公告)号：US06503784B1

公开(公告)日：2003-01-07

申请号：US09670742

申请日：2000-09-27

申请人： Gerhard Enders ,  Thomas Schulz ,  Dietrich Widmann ,  Lothar Risch

发明人： Gerhard Enders ,  Thomas Schulz ,  Dietrich Widmann ,  Lothar Risch

IPC分类号： H01L218238

CPC分类号： H01L27/11 ,  H01L21/823885 ,  H01L27/092 ,  H01L27/1104 ,  H01L27/1203

摘要： A semiconductor body-having a pair of vertical, double-gated CMOS transistors. An insulating layer extending horizontally beneath the surface of the semiconductor body such insulating layer being disposed beneath the pair of transistors. The transistors, together with additional such transistors, are arranged to form a Synchronous Dynamic Random Access Memory (SRAM) array. The array includes a plurality of SRAM cells arranged in rows and columns, each one of the cells having a WORDLINE connected to a WORLDINE CONTACT. The WORDLINE CONTACT is common to four contiguous one of the cells. One of the cells having a plurality of electrically interconnected MOS transistors arranged to provide an SRAM circuit. Each one of the cells has a VDD CONTACT and a VSS CONTACT. One of such CONTACTs is disposed centrally within each one of the cells and the other one of the CONTACTs being common to four contiguous ones of the cells. Each one of the cells has the common one of the CONTACTs and the WORDLINE CONTACT disposed at peripheral, corner regions of the cell.

摘要翻译： 一种具有一对垂直双门控CMOS晶体管的半导体体。 在半导体本体的表面下水平延伸的绝缘层，该绝缘层设置在该对晶体管的下方。 晶体管与附加的这种晶体管一起被布置成形成同步动态随机存取存储器（SRAM）阵列。 阵列包括以行和列排列的多个SRAM单元，每个单元都具有连接到WORLDINE CONTACT的WORDLINE。 WORDLINE CONTACT是四个连续的一个单元格共同的。 具有多个电互连的MOS晶体管的单元之一被布置成提供SRAM电路。 每个单元都有一个VDD CONTACT和一个VSS CONTACT。 这种CONTACT之一被布置在每个单元格的中心并且另一个CONTACT被四个相邻的单元共同。 每个单元格具有共同的一个CONTACT和WORDLINE CONTACT放置在单元的外围角区域。

公开(公告)号：US06472767B1

公开(公告)日：2002-10-29

申请号：US09302757

申请日：1999-04-30

申请人： Gerhard Enders ,  Thomas Schulz ,  Dietrich Widmann ,  Lothar Risch

发明人： Gerhard Enders ,  Thomas Schulz ,  Dietrich Widmann ,  Lothar Risch

IPC分类号： H01L2711

CPC分类号： H01L27/11 ,  H01L27/1104

摘要： A semiconductor body having a pair of vertical, double-gated CMOS transistors. An insulating layer extending horizontally beneath the surface of the semiconductor body such insulating layer being disposed beneath the pair of transistors. The transistors, together with additional such transistors, are arranged to form a Synchronous Dynamic Random Access Memory (SRAM) array. The array includes a plurality of SRAM cells arranged in rows and columns, each one of the cells having a WORDLINE connected to a WORLDINE CONTACT. The WORDLINE CONTACT is common to four contiguous one of the cells. One of the cells having a plurality of electrically interconnected MOS transistors arranged to provide an SRAM circuit. Each one of the cells has a VDD CONTACT and a VSS CONTACT. One of such CONTACTs is disposed centrally within each one of the cells and the other one of the CONTACTs being common to four contiguous ones of the cells. Each one of the cells has the common one of the CONTACTs and the WORDLINE CONTACT disposed at peripheral, corner regions of the cell.

摘要翻译： 具有一对垂直双门控CMOS晶体管的半导体本体。 在半导体本体的表面下水平延伸的绝缘层，该绝缘层设置在该对晶体管的下方。 晶体管与附加的这种晶体管一起被布置成形成同步动态随机存取存储器（SRAM）阵列。 阵列包括以行和列排列的多个SRAM单元，每个单元都具有连接到WORLDINE CONTACT的WORDLINE。 WORDLINE CONTACT是四个连续的一个单元格共同的。 具有多个电互连的MOS晶体管的单元之一被布置成提供SRAM电路。 每个单元都有一个VDD CONTACT和一个VSS CONTACT。 这种CONTACT之一被布置在每个单元格的中心并且另一个CONTACT被四个相邻的单元共同。 每个单元格具有共同的一个CONTACT和WORDLINE CONTACT放置在单元的外围角区域。

公开(公告)号：US06909141B2

公开(公告)日：2005-06-21

申请号：US10047013

申请日：2002-01-16

申请人： Wolfgang Rösner ,  Thomas Schulz ,  Lothar Risch ,  Thomas Äugle ,  Herbert Schäfer ,  Martin Franosch

发明人： Wolfgang Rösner ,  Thomas Schulz ,  Lothar Risch ,  Thomas Äugle ,  Herbert Schäfer ,  Martin Franosch

IPC分类号： H01L21/335 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/76 ,  H01L51/00 ,  H01L51/05 ,  H01L51/30 ,  H01L21/8238

CPC分类号： B82Y10/00 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/7613 ,  H01L51/0048 ,  H01L51/0052 ,  H01L51/0512

摘要： A vertical semiconductor transistor component is built up on a substrate by using a statistical mask. The vertical semiconductor transistor component has vertical pillar structures statistically distributed over the substrate. The vertical pillar structures are electrically connected on a base side thereof to a first common electrical contact. The vertical pillar structures include, along the vertical direction, layer zones of differing conductivity, and have insulation layers on their circumferential walls. An electrically conductive material is deposited between the pillar structures and forms a second electrical contact of the semiconductor transistor component. The pillar structures are electrically contacted to a third common electrical contact on their capping side.

摘要翻译： 通过使用统计掩模在衬底上构建垂直半导体晶体管组件。 垂直半导体晶体管组件具有统计分布在衬底上的垂直柱结构。 垂直柱结构在其基极侧电连接到第一公共电接触。 垂直柱结构沿垂直方向包括不同导电性的层区，并且在其周壁上具有绝缘层。 导电材料沉积在柱结构之间并形成半导体晶体管组件的第二电接触。 支柱结构在其封盖侧与第三公共电触头电接触。

公开(公告)号：US06614069B2

公开(公告)日：2003-09-02

申请号：US10054440

申请日：2002-01-22

申请人： Wolfgang Rösner ,  Thomas Schulz ,  Lothar Risch ,  Ties Ramcke

发明人： Wolfgang Rösner ,  Thomas Schulz ,  Lothar Risch ,  Ties Ramcke

IPC分类号： H01L29788

CPC分类号： B82Y10/00 ,  H01L21/28273 ,  H01L29/7887 ,  H01L29/7888

摘要： A nonvolatile semiconductor memory cell includes a transistor component formed on a substrate and a storage node that determines the switching state of the transistor component. The storage node is arranged near a control gate electrode. The storage node has a group of vertically oriented column structures having at least two semiconductor layer zones and an insulating layer zone situated between the two semiconductor layer zones.