公开(公告)号：US06909141B2

公开(公告)日：2005-06-21

申请号：US10047013

申请日：2002-01-16

申请人： Wolfgang Rösner ,  Thomas Schulz ,  Lothar Risch ,  Thomas Äugle ,  Herbert Schäfer ,  Martin Franosch

发明人： Wolfgang Rösner ,  Thomas Schulz ,  Lothar Risch ,  Thomas Äugle ,  Herbert Schäfer ,  Martin Franosch

IPC分类号： H01L21/335 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/76 ,  H01L51/00 ,  H01L51/05 ,  H01L51/30 ,  H01L21/8238

CPC分类号： B82Y10/00 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/7613 ,  H01L51/0048 ,  H01L51/0052 ,  H01L51/0512

摘要： A vertical semiconductor transistor component is built up on a substrate by using a statistical mask. The vertical semiconductor transistor component has vertical pillar structures statistically distributed over the substrate. The vertical pillar structures are electrically connected on a base side thereof to a first common electrical contact. The vertical pillar structures include, along the vertical direction, layer zones of differing conductivity, and have insulation layers on their circumferential walls. An electrically conductive material is deposited between the pillar structures and forms a second electrical contact of the semiconductor transistor component. The pillar structures are electrically contacted to a third common electrical contact on their capping side.

摘要翻译： 通过使用统计掩模在衬底上构建垂直半导体晶体管组件。 垂直半导体晶体管组件具有统计分布在衬底上的垂直柱结构。 垂直柱结构在其基极侧电连接到第一公共电接触。 垂直柱结构沿垂直方向包括不同导电性的层区，并且在其周壁上具有绝缘层。 导电材料沉积在柱结构之间并形成半导体晶体管组件的第二电接触。 支柱结构在其封盖侧与第三公共电触头电接触。

公开(公告)号：US06614069B2

公开(公告)日：2003-09-02

申请号：US10054440

申请日：2002-01-22

申请人： Wolfgang Rösner ,  Thomas Schulz ,  Lothar Risch ,  Ties Ramcke

发明人： Wolfgang Rösner ,  Thomas Schulz ,  Lothar Risch ,  Ties Ramcke

IPC分类号： H01L29788

CPC分类号： B82Y10/00 ,  H01L21/28273 ,  H01L29/7887 ,  H01L29/7888

摘要： A nonvolatile semiconductor memory cell includes a transistor component formed on a substrate and a storage node that determines the switching state of the transistor component. The storage node is arranged near a control gate electrode. The storage node has a group of vertically oriented column structures having at least two semiconductor layer zones and an insulating layer zone situated between the two semiconductor layer zones.

公开(公告)号：US06864129B2

公开(公告)日：2005-03-08

申请号：US09996279

申请日：2001-11-28

申请人： Lothar Risch ,  Wolfgang Rösner ,  Thomas Schulz

发明人： Lothar Risch ,  Wolfgang Rösner ,  Thomas Schulz

IPC分类号： H01L29/417 ,  H01L21/20 ,  H01L21/336 ,  H01L29/786 ,  H01L21/00 ,  H01L27/01

CPC分类号： H01L29/66772 ,  H01L29/78648

摘要： A double gate MOSFET transistor and a method for fabricating it are described. In this case, a semiconductor layer structure of a transistor channel to be formed is embedded in a spacer material and contact-connected by source and drain regions which are filled into depressions that are etched on opposite sides of the semiconductor layer structure. Afterwards, the spacer material is etched out selectively and replaced by the electrically conductive gate electrode material.

摘要翻译： 描述双栅极MOSFET晶体管及其制造方法。 在这种情况下，要形成的晶体管沟道的半导体层结构被嵌入到间隔物材料中，并且被源极和漏极区域接触，其被填充到在半导体层结构的相对侧被蚀刻的凹陷中。 之后，间隔材料被选择性蚀刻掉，并由导电栅电极材料代替。

公开(公告)号：US06362502B1

公开(公告)日：2002-03-26

申请号：US09692118

申请日：2000-10-19

申请人： Wolfgang Rösner ,  Thomas Schulz ,  Lothar Risch ,  Franz Hofmann

发明人： Wolfgang Rösner ,  Thomas Schulz ,  Lothar Risch ,  Franz Hofmann

IPC分类号： H01L27108

CPC分类号： H01L27/1203 ,  H01L27/108 ,  H01L27/10876

摘要： A memory cell contains a memory transistor and a transfer transistor. A gate electrode of the transfer transistor and a control gate electrode of the memory transistor are connected to a word line. The memory transistor has a floating gate electrode that is isolated from a channel region of the memory transistor by a first dielectric layer and is connected to a first source/drain region of the transfer transistor. The control gate electrode is isolated from the floating gate electrode by a second dielectric layer. A first source/drain region of the memory transistor is connected to a bit line. The memory and transfer transistors are preferably of different conductivity types. During the writing of information, the transfer transistor is in the on-state and the memory transistor is in the off-state. During the reading-out of information, the transfer transistor is in the off-state and the memory transistor is in the on-state.

摘要翻译： 存储单元包含存储晶体管和转移晶体管。 转移晶体管的栅电极和存储晶体管的控制栅电极连接到字线。 存储晶体管具有通过第一介电层与存储晶体管的沟道区隔离并与转移晶体管的第一源极/漏极区连接的浮栅电极。 控制栅电极通过第二电介质层与浮置栅电极隔离。 存储晶体管的第一源/漏区连接到位线。 存储器和转移晶体管优选地具有不同的导电类型。 在写入信息期间，传输晶体管处于导通状态，并且存储晶体管处于截止状态。 在读出信息期间，传输晶体管处于截止状态，并且存储晶体管处于导通状态。

公开(公告)号：US06337247B1

公开(公告)日：2002-01-08

申请号：US09487411

申请日：2000-01-18

申请人： Thomas Schulz ,  Thomas Äugle ,  Wolfgang Rösner ,  Lothar Risch

发明人： Thomas Schulz ,  Thomas Äugle ,  Wolfgang Rösner ,  Lothar Risch

IPC分类号： H01L21336

CPC分类号： H01L29/66666 ,  H01L29/7827 ,  H01L29/7834

摘要： A spacer is used as a mask in an etching step during which a layer structure is produced for a channel layer and for a first source/drain region. After the layer structure has been produced, the first source/drain region and a second source/drain region can be produced by implantation. The second source/drain region is self-aligned on two mutually opposite flanks of the layer structure. A gate electrode can be produced in the form of a spacer on the two flanks. In order to avoid a capacitance formed by a first contact of the gate electrode and the first source/drain region, a part of the first source/drain region may be removed. If the layer structure is produced along edges of an inner area, then a third contact of the second source/drain region may be produced inside the inner area in order to reduce the surface area of the transistor.

摘要翻译： 在蚀刻步骤中使用间隔物作为掩模，在该步骤中，为沟道层和第一源极/漏极区域产生层结构。 在生成层结构之后，可以通过注入产生第一源极/漏极区域和第二源极/漏极区域。 第二源极/漏极区域在层结构的两个相互相对的侧面上自对准。 可以在两个侧面上以间隔物的形式制造栅电极。 为了避免由栅极电极和第一源极/漏极区域的第一接触形成的电容，可以去除第一源极/漏极区域的一部分。 如果沿着内部区域的边缘产生层结构，则可以在内部区域内产生第二源极/漏极区域的第三接触，以便减小晶体管的表面积。

公开(公告)号：US06320447B1

公开(公告)日：2001-11-20

申请号：US09707032

申请日：2000-11-06

申请人： Wolfgang Rösner ,  Ties Ramcke ,  Lothar Risch

发明人： Wolfgang Rösner ,  Ties Ramcke ,  Lothar Risch

IPC分类号： H03K1762

CPC分类号： G06F7/527 ,  B82Y10/00 ,  G06F7/502 ,  G06F7/505 ,  G06F2207/4828 ,  H03K19/08 ,  Y10S977/936 ,  Y10S977/937 ,  Y10S977/94

摘要： The circuit configuration has at least five single-electron transistors, three of which are connected via a second main node and a third main node between a first main node and an output. The fourth single-electron transistor is connected between the second main node and a first supply voltage, with its gate electrode being connected to the first main node. The fifth single-electron transistor is connected between the third main node and the first supply voltage, with its gate electrode being connected to the second main node. The circuit configuration is suitable for use as a full adder and as a multiplier.

摘要翻译： 电路配置具有至少五个单电子晶体管，其中三个通过第二主节点和第一主节点与输出端之间的第三主节点连接。 第四单电子晶体管连接在第二主节点和第一电源电压之间，其栅电极连接到第一主节点。 第五单电晶体管连接在第三主节点和第一电源电压之间，其栅电极连接到第二主节点。 电路配置适合用作全加器和乘法器。

公开(公告)号：US06229169B1

公开(公告)日：2001-05-08

申请号：US09213724

申请日：1998-12-17

申请人： Franz Hofmann ,  Wolfgang Krautschneider ,  Wolfgang Rösner ,  Lothar Risch ,  Till Schlösser ,  Paul-Werner Basse

发明人： Franz Hofmann ,  Wolfgang Krautschneider ,  Wolfgang Rösner ,  Lothar Risch ,  Till Schlösser ,  Paul-Werner Basse

IPC分类号： H01L27108

CPC分类号： H01L27/11502 ,  H01L27/108 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/115 ,  H01L27/11507

摘要： A memory cell configuration contains a multiplicity of memory cells in a semiconductor substrate. Each of the memory cells has a selection transistor connected between a bit line and a storage element. The memory cells can each be driven via a first word line and a second word line, the first word line and the second word line crossing one another. The memory cell configuration is, in particular, a DRAM configuration.

摘要翻译： 存储单元配置在半导体衬底中包含多个存储单元。 每个存储单元具有连接在位线和存储元件之间的选择晶体管。 每个存储器单元可以通过第一字线和第二字线驱动，第一字线和第二字线彼此交叉。 存储单元配置尤其是DRAM配置。

公开(公告)号：US06490190B1

公开(公告)日：2002-12-03

申请号：US09528159

申请日：2000-03-17

申请人： Ties Ramcke ,  Wolfgang Rösner ,  Lothar Risch

发明人： Ties Ramcke ,  Wolfgang Rösner ,  Lothar Risch

IPC分类号： G11C1100

CPC分类号： G11C11/16 ,  G11C15/02 ,  G11C15/046

摘要： A memory cell configuration has word lines and bit lines that extend transversely with respect thereto. Memory elements with a giant magnetoresistive effect are respectively connected between one of the word lines and one of the bit lines. The bit lines are each connected to a sense amplifier by means of which the potential on the respective bit line can be regulated to a reference potential and at which an output signal can be picked off. The memory cell configuration can be used both as an MRAM and as an associative memory.

摘要翻译： 存储单元配置具有相对于其横向延伸的字线和位线。 具有巨磁阻效应的存储元件分别连接在一条字线和一条位线之间。 位线各自连接到读出放大器，通过该读出放大器可以将相应位线上的电位调节到参考电位，并且可以在其上拾取输出信号。 存储单元配置可以用作MRAM和关联存储器。

公开(公告)号：US07368752B2

公开(公告)日：2008-05-06

申请号：US10839800

申请日：2004-05-06

申请人： Richard J. Luyken ,  Franz Hofmann ,  Lothar Risch ,  Dirk Manger ,  Wolfgang Rösner ,  Till Schlösser ,  Michael Specht

发明人： Richard J. Luyken ,  Franz Hofmann ,  Lothar Risch ,  Dirk Manger ,  Wolfgang Rösner ,  Till Schlösser ,  Michael Specht

IPC分类号： H01L27/108 ,  H01L29/12 ,  H01L31/112

CPC分类号： H01L27/10823 ,  H01L27/10808 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10891 ,  H01L29/7851

摘要： A DRAM memory cell is provided with a selection transistor, which is arranged horizontally at a semiconductor substrate surface and has a first source/drain electrode, a second source/drain electrode, a channel layer arranged between the first and the second source/drain electrode in the semiconductor substrate, and a gate electrode, which is arranged along the channel layer and is electrically insulated from the channel layer, a storage capacitor, which has a first capacitor electrode and a second capacitor electrode, insulated from the first capacitor electrode, one of the capacitor electrodes of the storage capacitor being electrically conductively connected to one of the source/drain electrodes of the selection transistor, and a semiconductor substrate electrode on the rear side, the gate electrode enclosing the channel layer at at least two opposite sides.

摘要翻译： DRAM存储单元设置有选择晶体管，该晶体管被水平地布置在半导体衬底表面处并且具有第一源极/漏极，第二源极/漏极，布置在第一和第二源极/漏极之间的沟道层 在所述半导体基板中，沿着所述沟道层配置并与所述沟道层电绝缘的栅电极具有与所述第一电容电极绝缘的第一电容电极和第二电容电极的保持电容器， 所述存储电容器的电容器电极与所述选择晶体管的源极/漏极之一导电地连接，并且在后侧具有半导体衬底电极，所述栅电极在至少两个相对的两侧包围所述沟道层。

公开(公告)号：US06442042B2

公开(公告)日：2002-08-27

申请号：US09883901

申请日：2001-06-18

申请人： Ties Ramcke ,  Lothar Risch ,  Wolfgang Rösner

发明人： Ties Ramcke ,  Lothar Risch ,  Wolfgang Rösner

IPC分类号： H05K702

CPC分类号： H01L23/528 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

摘要： At least one CMOS component which is configured in a semiconductor substrate is part of the inventive circuit assembly. An insulating layer is configured on the semiconductor substrate. The insulating layer covers the CMOS component. A nanoelectronic component is configured above the insulating layer. At least one conducting structure is configured in the insulating layer and serves to link the nanoelectronic component with the CMOS component. If several nanoelectronic components are provided, they are preferably grouped to nano-circuit blocks. Each of the nano-circuit blocks is so small that the RC times of their lines do not exceed 1 ns.

摘要翻译： 配置在半导体衬底中的至少一个CMOS部件是本发明电路组件的一部分。 绝缘层配置在半导体衬底上。 绝缘层覆盖CMOS元件。 纳米电子部件被配置在绝缘层的上方。 在绝缘层中配置至少一个导电结构，用于将纳米电子部件与CMOS部件连接起来。 如果提供几个纳米电子部件，则它们优选地分组成纳米电路块。 每个纳米电路块都很小，使得它们的线路的RC时间不超过1ns。