公开(公告)号：US06459123B1

公开(公告)日：2002-10-01

申请号：US09302768

申请日：1999-04-30

申请人： Gerhard Enders ,  Thomas Schulz ,  Dietrich Widmann ,  Lothar Risch

发明人： Gerhard Enders ,  Thomas Schulz ,  Dietrich Widmann ,  Lothar Risch

IPC分类号： H01L2994

CPC分类号： H01L27/11 ,  H01L21/823885 ,  H01L27/092 ,  H01L27/1104 ,  H01L27/1203

摘要： A semiconductor body having a pair of vertical, double-gated CMOS transistors. An insulating layer extending horizontally beneath the surface of the semiconductor body such insulating layer being disposed beneath the pair of transistors. The transistors, together with additional such transistors, are arranged to form a Synchronous Dynamic Random Access Memory (SRAM) array. The array includes a plurality of SRAM cells arranged in rows and columns, each one of the cells having a WORDLINE connected to a WORLDINE CONTACT. The WORDLINE CONTACT is common to four contiguous one of the cells. One of the cells having a plurality of electrically interconnected MOS transistors arranged to provide an SRAM circuit. Each one of the cells has a VDD CONTACT and a VSS CONTACT. One of such CONTACTs is disposed centrally within each one of the cells and the other one of the CONTACTs being common to four contiguous ones of the cells. Each one of the cells has the common one of the CONTACTs and the WORDLINE CONTACT disposed at peripheral, corner regions of the cell.

摘要翻译： 具有一对垂直双门控CMOS晶体管的半导体本体。 在半导体本体的表面下水平延伸的绝缘层，该绝缘层设置在该对晶体管的下方。 晶体管与附加的这种晶体管一起被布置成形成同步动态随机存取存储器（SRAM）阵列。 阵列包括以行和列排列的多个SRAM单元，每个单元都具有连接到WORLDINE CONTACT的WORDLINE。 WORDLINE CONTACT是四个连续的一个单元格共同的。 具有多个电互连的MOS晶体管的单元之一被布置成提供SRAM电路。 每个单元都有一个VDD CONTACT和一个VSS CONTACT。 这种CONTACT之一被布置在每个单元格的中心并且另一个CONTACT被四个相邻的单元共同。 每个单元格具有共同的一个CONTACT和WORDLINE CONTACT放置在单元的外围角区域。

公开(公告)号：US06503784B1

公开(公告)日：2003-01-07

申请号：US09670742

申请日：2000-09-27

申请人： Gerhard Enders ,  Thomas Schulz ,  Dietrich Widmann ,  Lothar Risch

发明人： Gerhard Enders ,  Thomas Schulz ,  Dietrich Widmann ,  Lothar Risch

IPC分类号： H01L218238

CPC分类号： H01L27/11 ,  H01L21/823885 ,  H01L27/092 ,  H01L27/1104 ,  H01L27/1203

摘要： A semiconductor body-having a pair of vertical, double-gated CMOS transistors. An insulating layer extending horizontally beneath the surface of the semiconductor body such insulating layer being disposed beneath the pair of transistors. The transistors, together with additional such transistors, are arranged to form a Synchronous Dynamic Random Access Memory (SRAM) array. The array includes a plurality of SRAM cells arranged in rows and columns, each one of the cells having a WORDLINE connected to a WORLDINE CONTACT. The WORDLINE CONTACT is common to four contiguous one of the cells. One of the cells having a plurality of electrically interconnected MOS transistors arranged to provide an SRAM circuit. Each one of the cells has a VDD CONTACT and a VSS CONTACT. One of such CONTACTs is disposed centrally within each one of the cells and the other one of the CONTACTs being common to four contiguous ones of the cells. Each one of the cells has the common one of the CONTACTs and the WORDLINE CONTACT disposed at peripheral, corner regions of the cell.

摘要翻译： 一种具有一对垂直双门控CMOS晶体管的半导体体。 在半导体本体的表面下水平延伸的绝缘层，该绝缘层设置在该对晶体管的下方。 晶体管与附加的这种晶体管一起被布置成形成同步动态随机存取存储器（SRAM）阵列。 阵列包括以行和列排列的多个SRAM单元，每个单元都具有连接到WORLDINE CONTACT的WORDLINE。 WORDLINE CONTACT是四个连续的一个单元格共同的。 具有多个电互连的MOS晶体管的单元之一被布置成提供SRAM电路。 每个单元都有一个VDD CONTACT和一个VSS CONTACT。 这种CONTACT之一被布置在每个单元格的中心并且另一个CONTACT被四个相邻的单元共同。 每个单元格具有共同的一个CONTACT和WORDLINE CONTACT放置在单元的外围角区域。

公开(公告)号：US06472767B1

公开(公告)日：2002-10-29

申请号：US09302757

申请日：1999-04-30

申请人： Gerhard Enders ,  Thomas Schulz ,  Dietrich Widmann ,  Lothar Risch

发明人： Gerhard Enders ,  Thomas Schulz ,  Dietrich Widmann ,  Lothar Risch

IPC分类号： H01L2711

CPC分类号： H01L27/11 ,  H01L27/1104

摘要： A semiconductor body having a pair of vertical, double-gated CMOS transistors. An insulating layer extending horizontally beneath the surface of the semiconductor body such insulating layer being disposed beneath the pair of transistors. The transistors, together with additional such transistors, are arranged to form a Synchronous Dynamic Random Access Memory (SRAM) array. The array includes a plurality of SRAM cells arranged in rows and columns, each one of the cells having a WORDLINE connected to a WORLDINE CONTACT. The WORDLINE CONTACT is common to four contiguous one of the cells. One of the cells having a plurality of electrically interconnected MOS transistors arranged to provide an SRAM circuit. Each one of the cells has a VDD CONTACT and a VSS CONTACT. One of such CONTACTs is disposed centrally within each one of the cells and the other one of the CONTACTs being common to four contiguous ones of the cells. Each one of the cells has the common one of the CONTACTs and the WORDLINE CONTACT disposed at peripheral, corner regions of the cell.

摘要翻译： 具有一对垂直双门控CMOS晶体管的半导体本体。 在半导体本体的表面下水平延伸的绝缘层，该绝缘层设置在该对晶体管的下方。 晶体管与附加的这种晶体管一起被布置成形成同步动态随机存取存储器（SRAM）阵列。 阵列包括以行和列排列的多个SRAM单元，每个单元都具有连接到WORLDINE CONTACT的WORDLINE。 WORDLINE CONTACT是四个连续的一个单元格共同的。 具有多个电互连的MOS晶体管的单元之一被布置成提供SRAM电路。 每个单元都有一个VDD CONTACT和一个VSS CONTACT。 这种CONTACT之一被布置在每个单元格的中心并且另一个CONTACT被四个相邻的单元共同。 每个单元格具有共同的一个CONTACT和WORDLINE CONTACT放置在单元的外围角区域。

公开(公告)号：US06262448B1

公开(公告)日：2001-07-17

申请号：US09302756

申请日：1999-04-30

申请人： Gerhard Enders ,  Matthias Ilg ,  Lothar Risch ,  Dietrich Widmann

发明人： Gerhard Enders ,  Matthias Ilg ,  Lothar Risch ,  Dietrich Widmann

IPC分类号： H01L27108

CPC分类号： H01L27/10864 ,  H01L27/10841 ,  H01L27/10876

摘要： A DRAM cell is disposed in an electrically isolated region of a semiconductor body. The cell includes a storage capacitor disposed in a trench. The capacitor is disposed entirely within the isolated region of the semiconductor body. The cell includes a transistor disposed in the isolated region. The transistor has a pair of gates. A word line is provided for addressing the cell. The word line has an electrical contact region to the transistor. The word line contact region is disposed entirely within the isolated region of the semiconductor body. The transistor has an active area. The active area has source, drain, and channel regions. The active area is disposed entirely within the isolated region of the semiconductor body. A bit line is provided for the cell. The bit line is in electrical contact with the gates of the transistor at a pair of bit line contact regions. Both such bit line contact regions are disposed entirely within the isolated region of the cell. With such an arrangement a DRAM cell is provided having a relatively occupies a relatively small amount of surface area of the semiconductor body.

摘要翻译： DRAM单元设置在半导体本体的电隔离区域中。 电池包括设置在沟槽中的存储电容器。 电容器完全设置在半导体本体的隔离区域内。 电池包括设置在隔离区域中的晶体管。 晶体管有一对门。 提供字线用于寻址单元。 字线具有到晶体管的电接触区域。 字线接触区域完全设置在半导体本体的隔离区域内。 晶体管有一个有源区。 有源区域有源极，漏极和沟道区域。 有源区域完全设置在半导体本体的隔离区域内。 为单元提供位线。 位线在一对位线接触区域与晶体管的栅极电接触。 两个这样的位线接触区域完全设置在电池的隔离区域内。 通过这样的布置，提供了DRAM单元，其具有相对占据半导体本体的较小量的表面积。

公开(公告)号：US06319787B1

公开(公告)日：2001-11-20

申请号：US09107980

申请日：1998-06-30

申请人： Gerhard Enders ,  Matthias Ilg ,  Dietrich Widmann

发明人： Gerhard Enders ,  Matthias Ilg ,  Dietrich Widmann

IPC分类号： H01L2120

CPC分类号： H01L27/10861 ,  H01L27/10829

摘要： A trench capacitor having a substrate with a trench extending therein with a nested, e.g., concentric, conductive regions disposed within the trench. A dielectric material is disposed within the substrate. The dielectric material has portions thereof disposed between the concentric conductive regions to dielectrically electrically separate one of the conductive regions from another one of the conductive regions. The dielectrically separated conductive regions provide a pair of electrodes for the capacitor. Selected ones of the concentric conductive regions are electrically connected to provide one of the electrodes for the capacitor. The substrate has a conductive region therein and one of the concentric conductive regions providing one of the electrodes is electrically connected to the conductive region in the substrate. One of the concentric conductive regions is electrically connected to a conductive region in the substrate through a bottom portion of the trench.

摘要翻译： 一种沟槽式电容器，其具有在其中延伸有沟槽的衬底，其具有设置在沟槽内的嵌套的，例如同心的导电区域。 电介质材料设置在衬底内。 电介质材料具有设置在同心导电区域之间的部分，以将导电区域中的一个与另一个导电区域电介质电分离。 介电分离的导电区域为电容器提供一对电极。 选择的同心导电区域被电连接以提供用于电容器的电极之一。 衬底在其中具有导电区域，并且提供电极之一的同心导电区域中的一个电连接到衬底中的导电区域。 一个同心导电区域通过沟槽的底部电连接到衬底中的导电区域。

公开(公告)号：US6124156A

公开(公告)日：2000-09-26

申请号：US27015

申请日：1998-02-20

申请人： Dietrich Widmann ,  Martin Kerber

发明人： Dietrich Widmann ,  Martin Kerber

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/10 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L21/823814 ,  H01L21/76294 ,  H01L27/092 ,  H01L29/1083 ,  H01L29/7833

摘要： A CMOS circuit has all-around dielectrically insulated source-drain regions. Trenches are formed in the source-drain regions. The trenches are etched into the mono-crystalline silicon and filled with undoped or very lightly doped silicon. The completely or nearly completely depleted silicon in the trenches represents a dielectrically insulating layer and insulates the source-drain regions towards the adjacent silicon substrate.

摘要翻译： CMOS电路具有全面的介电绝缘源极 - 漏极区域。 在源极 - 漏极区域中形成沟槽。 将沟槽蚀刻到单晶硅中，并填充未掺杂或非常轻掺杂的硅。 沟槽中完全或几乎完全耗尽的硅代表介电绝缘层，并使源极 - 漏极区域朝相邻的硅衬底绝缘。

公开(公告)号：US4351100A

公开(公告)日：1982-09-28

申请号：US187774

申请日：1980-09-16

申请人： Dietrich Widmann

发明人： Dietrich Widmann

IPC分类号： H01L29/762 ,  H01L21/339 ,  H01L21/8234 ,  H01L21/20 ,  H01L21/283

CPC分类号： H01L29/66954 ,  H01L21/823406

摘要： In an exemplary embodiment, a first polysilicon layer is provided with a SiO.sub.2 mask, and the first polysilicon layer is etched away under the SiO.sub.2 mask to produce SiO.sub.2 overhangs of a lateral extent corresponding to about twice the edge position error (.sup..+-. s). Then when second polysilicon layers are produced by means of chemical vapor deposition (CVD), to occupy the cavities under the SiO.sub.2 overhangs, the desired nonoverlapping poly-Si-2 electrodes result after definition of those poly-Si-2 electrodes by known lithographical techniques.

摘要翻译： 在示例性实施例中，第一多晶硅层设置有SiO 2掩模，并且在SiO 2掩模下蚀刻掉第一多晶硅层以产生对应于约两倍边缘位置误差（+/- s）的横向范围的SiO 2突出端， 。 然后当通过化学气相沉积（CVD）产生第二多晶硅层时，为了占据SiO 2突出部下的空腔，在通过已知的光刻技术定义那些多晶硅二极管后，产生所需的非重叠多晶硅二极管 。

公开(公告)号：US4356622A

公开(公告)日：1982-11-02

申请号：US157495

申请日：1980-06-09

申请人： Dietrich Widmann

发明人： Dietrich Widmann

IPC分类号： H01L27/04 ,  H01L21/033 ,  H01L21/28 ,  H01L21/321 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/10 ,  H01L29/78 ,  H01L21/225 ,  H01L21/283

CPC分类号： H01L21/321 ,  H01L21/033 ,  H01L21/76889 ,  H01L21/8234 ,  Y10S148/141 ,  Y10S438/934

摘要： Low-resistance diffused regions useful as current-supply paths in IC MOS semiconductor circuits in silicon-gate technology are produced by forming a metal silicide on a doped polysilicon layer positioned on a substrate, applying a SiO.sub.2 layer over the silicide layer, structuring the resultant SiO.sub.2 -silicide-polysilicon triple layer in such a manner that areas of the substrate where the low resistance diffused regions are desired remain covered, thereafter executing gate oxidation and completing fabrication of the desired circuit.

摘要翻译： 通过在位于衬底上的掺杂多晶硅层上形成金属硅化物，在硅化物层上施加SiO 2层，从而构成所得的结构，从而产生用作硅栅极技术中IC MOS半导体电路中的电流供应路径的低电阻扩散区域 SiO 2 - 硅化物 - 多晶硅三层层，其中需要保持低电阻扩散区域的衬底的面积保持覆盖，然后执行栅极氧化并完成所需电路的制造。

公开(公告)号：US4352237A

公开(公告)日：1982-10-05

申请号：US187773

申请日：1980-09-16

申请人： Dietrich Widmann

发明人： Dietrich Widmann

IPC分类号： H01L29/762 ,  H01L21/339 ,  H01L21/8234 ,  H01L21/20 ,  H01L21/283

CPC分类号： H01L29/66954 ,  H01L21/823406 ,  Y10S438/911

摘要： In an exemplary embodiment, after underetching a first polysilicon layer beneath spaced SiO.sub.2 cover layers to produce pairs of confronting SiO.sub.2 overhangs with gaps therebetween, and providing an insulating layer at the end faces of the spaced poly-Si-1 electrodes formed from the first polysilicon layer, a second polysilicon layer is produced by chemical vapor deposition (CVD) so as to fill the cavities beneath the SiO.sub.2 overhangs via the gaps between each pair of confronting overhangs. The second polysilicon layer is then etched away so as to leave intervening self-adjusting, nonoverlapping poly-Si-2 electrodes formed from the second polysilicon layer with surfaces terminating for example slightly below the upper surfaces of the SiO.sub.2 cover layers. For a center-to-center spacing of poly-Si-1 electrodes of six microns, the SiO.sub.2 overhangs may have an extent (e.g. 0.7 microns) about equal to the electrode layer thickness (e.g. 0.8 microns).

摘要翻译： 在一个示例性实施例中，在将第二多晶硅层放置在间隔开的SiO 2覆盖层之下以产生成对的相对间隔的间隔开的SiO 2悬垂线之后，并且在由第一多晶硅形成的间隔开的多晶Si-1电极的端面处提供绝缘层 层，通过化学气相沉积（CVD）产生第二多晶硅层，以便通过每对相对的突出端之间的间隙填充SiO 2悬垂体下方的空腔。 然后蚀刻掉第二多晶硅层，以便留下由第二多晶硅层形成的介入的自调节的非重叠的多晶硅二极管，其表面终止于例如稍微低于SiO 2覆盖层的上表面。 对于六微米的多晶Si-1电极的中心到中心间隔，SiO 2悬垂部分可以具有等于电极层厚度（例如0.8微米）的程度（例如0.7微米）。

公开(公告)号：US06635388B1

公开(公告)日：2003-10-21

申请号：US09429837

申请日：1999-10-29

申请人： Christoph Friedrich ,  Uwe Griesinger ,  Rainer Pforr ,  Dietrich Widmann ,  Andreas Grassmann

发明人： Christoph Friedrich ,  Uwe Griesinger ,  Rainer Pforr ,  Dietrich Widmann ,  Andreas Grassmann

IPC分类号： G03F900

CPC分类号： G03F1/34 ,  G03F7/2022

摘要： The invention relates to a phase shift mask for lithographically producing small structures at the limit of a resolution that is predetermined by the wavelength of the exposure radiation. The phase shift mask has first regions A and second regions B that effect a phase-shift relative to the first regions. The second regions are arranged beside the first regions for producing a sudden phase shift along the boundaries between the first and the second regions. Individual first regions touch one another via corners at points, at which the second regions also touch one another via corners. The result is that the boundaries between first and second regions merge at these points and these points are opaque to the radiation. The invention makes it possible to expose extremely small contact holes with just a single exposure and thus leads to a reduction of costs in the fabrication of integrated semiconductor circuits.

摘要翻译： 本发明涉及一种用于光刻产生在由曝光辐射的波长预定的分辨率极限处的小结构的相移掩模。 相移掩模具有相对于第一区域进行相移的第一区域A和第二区域B. 第二区域布置在第一区域旁边，用于沿着第一和第二区域之间的边界产生突然的相移。 单个第一区域通过角点彼此接触，在第二区域也通过拐角彼此接触。 结果是第一和第二区域之间的边界在这些点处合并，并且这些点对辐射是不透明的。 本发明使得可以仅用一次曝光来暴露极小的接触孔，从而导致集成半导体电路的制造成本的降低。