公开(公告)号：US06503784B1

公开(公告)日：2003-01-07

申请号：US09670742

申请日：2000-09-27

申请人： Gerhard Enders ,  Thomas Schulz ,  Dietrich Widmann ,  Lothar Risch

发明人： Gerhard Enders ,  Thomas Schulz ,  Dietrich Widmann ,  Lothar Risch

IPC分类号： H01L218238

CPC分类号： H01L27/11 ,  H01L21/823885 ,  H01L27/092 ,  H01L27/1104 ,  H01L27/1203

摘要： A semiconductor body-having a pair of vertical, double-gated CMOS transistors. An insulating layer extending horizontally beneath the surface of the semiconductor body such insulating layer being disposed beneath the pair of transistors. The transistors, together with additional such transistors, are arranged to form a Synchronous Dynamic Random Access Memory (SRAM) array. The array includes a plurality of SRAM cells arranged in rows and columns, each one of the cells having a WORDLINE connected to a WORLDINE CONTACT. The WORDLINE CONTACT is common to four contiguous one of the cells. One of the cells having a plurality of electrically interconnected MOS transistors arranged to provide an SRAM circuit. Each one of the cells has a VDD CONTACT and a VSS CONTACT. One of such CONTACTs is disposed centrally within each one of the cells and the other one of the CONTACTs being common to four contiguous ones of the cells. Each one of the cells has the common one of the CONTACTs and the WORDLINE CONTACT disposed at peripheral, corner regions of the cell.

摘要翻译： 一种具有一对垂直双门控CMOS晶体管的半导体体。 在半导体本体的表面下水平延伸的绝缘层，该绝缘层设置在该对晶体管的下方。 晶体管与附加的这种晶体管一起被布置成形成同步动态随机存取存储器（SRAM）阵列。 阵列包括以行和列排列的多个SRAM单元，每个单元都具有连接到WORLDINE CONTACT的WORDLINE。 WORDLINE CONTACT是四个连续的一个单元格共同的。 具有多个电互连的MOS晶体管的单元之一被布置成提供SRAM电路。 每个单元都有一个VDD CONTACT和一个VSS CONTACT。 这种CONTACT之一被布置在每个单元格的中心并且另一个CONTACT被四个相邻的单元共同。 每个单元格具有共同的一个CONTACT和WORDLINE CONTACT放置在单元的外围角区域。

公开(公告)号：US06472767B1

公开(公告)日：2002-10-29

申请号：US09302757

申请日：1999-04-30

申请人： Gerhard Enders ,  Thomas Schulz ,  Dietrich Widmann ,  Lothar Risch

发明人： Gerhard Enders ,  Thomas Schulz ,  Dietrich Widmann ,  Lothar Risch

IPC分类号： H01L2711

CPC分类号： H01L27/11 ,  H01L27/1104

摘要： A semiconductor body having a pair of vertical, double-gated CMOS transistors. An insulating layer extending horizontally beneath the surface of the semiconductor body such insulating layer being disposed beneath the pair of transistors. The transistors, together with additional such transistors, are arranged to form a Synchronous Dynamic Random Access Memory (SRAM) array. The array includes a plurality of SRAM cells arranged in rows and columns, each one of the cells having a WORDLINE connected to a WORLDINE CONTACT. The WORDLINE CONTACT is common to four contiguous one of the cells. One of the cells having a plurality of electrically interconnected MOS transistors arranged to provide an SRAM circuit. Each one of the cells has a VDD CONTACT and a VSS CONTACT. One of such CONTACTs is disposed centrally within each one of the cells and the other one of the CONTACTs being common to four contiguous ones of the cells. Each one of the cells has the common one of the CONTACTs and the WORDLINE CONTACT disposed at peripheral, corner regions of the cell.

摘要翻译： 具有一对垂直双门控CMOS晶体管的半导体本体。 在半导体本体的表面下水平延伸的绝缘层，该绝缘层设置在该对晶体管的下方。 晶体管与附加的这种晶体管一起被布置成形成同步动态随机存取存储器（SRAM）阵列。 阵列包括以行和列排列的多个SRAM单元，每个单元都具有连接到WORLDINE CONTACT的WORDLINE。 WORDLINE CONTACT是四个连续的一个单元格共同的。 具有多个电互连的MOS晶体管的单元之一被布置成提供SRAM电路。 每个单元都有一个VDD CONTACT和一个VSS CONTACT。 这种CONTACT之一被布置在每个单元格的中心并且另一个CONTACT被四个相邻的单元共同。 每个单元格具有共同的一个CONTACT和WORDLINE CONTACT放置在单元的外围角区域。

公开(公告)号：US06459123B1

公开(公告)日：2002-10-01

申请号：US09302768

申请日：1999-04-30

申请人： Gerhard Enders ,  Thomas Schulz ,  Dietrich Widmann ,  Lothar Risch

发明人： Gerhard Enders ,  Thomas Schulz ,  Dietrich Widmann ,  Lothar Risch

IPC分类号： H01L2994

CPC分类号： H01L27/11 ,  H01L21/823885 ,  H01L27/092 ,  H01L27/1104 ,  H01L27/1203

摘要： A semiconductor body having a pair of vertical, double-gated CMOS transistors. An insulating layer extending horizontally beneath the surface of the semiconductor body such insulating layer being disposed beneath the pair of transistors. The transistors, together with additional such transistors, are arranged to form a Synchronous Dynamic Random Access Memory (SRAM) array. The array includes a plurality of SRAM cells arranged in rows and columns, each one of the cells having a WORDLINE connected to a WORLDINE CONTACT. The WORDLINE CONTACT is common to four contiguous one of the cells. One of the cells having a plurality of electrically interconnected MOS transistors arranged to provide an SRAM circuit. Each one of the cells has a VDD CONTACT and a VSS CONTACT. One of such CONTACTs is disposed centrally within each one of the cells and the other one of the CONTACTs being common to four contiguous ones of the cells. Each one of the cells has the common one of the CONTACTs and the WORDLINE CONTACT disposed at peripheral, corner regions of the cell.

摘要翻译： 具有一对垂直双门控CMOS晶体管的半导体本体。 在半导体本体的表面下水平延伸的绝缘层，该绝缘层设置在该对晶体管的下方。 晶体管与附加的这种晶体管一起被布置成形成同步动态随机存取存储器（SRAM）阵列。 阵列包括以行和列排列的多个SRAM单元，每个单元都具有连接到WORLDINE CONTACT的WORDLINE。 WORDLINE CONTACT是四个连续的一个单元格共同的。 具有多个电互连的MOS晶体管的单元之一被布置成提供SRAM电路。 每个单元都有一个VDD CONTACT和一个VSS CONTACT。 这种CONTACT之一被布置在每个单元格的中心并且另一个CONTACT被四个相邻的单元共同。 每个单元格具有共同的一个CONTACT和WORDLINE CONTACT放置在单元的外围角区域。

公开(公告)号：US06262448B1

公开(公告)日：2001-07-17

申请号：US09302756

申请日：1999-04-30

申请人： Gerhard Enders ,  Matthias Ilg ,  Lothar Risch ,  Dietrich Widmann

发明人： Gerhard Enders ,  Matthias Ilg ,  Lothar Risch ,  Dietrich Widmann

IPC分类号： H01L27108

CPC分类号： H01L27/10864 ,  H01L27/10841 ,  H01L27/10876

摘要： A DRAM cell is disposed in an electrically isolated region of a semiconductor body. The cell includes a storage capacitor disposed in a trench. The capacitor is disposed entirely within the isolated region of the semiconductor body. The cell includes a transistor disposed in the isolated region. The transistor has a pair of gates. A word line is provided for addressing the cell. The word line has an electrical contact region to the transistor. The word line contact region is disposed entirely within the isolated region of the semiconductor body. The transistor has an active area. The active area has source, drain, and channel regions. The active area is disposed entirely within the isolated region of the semiconductor body. A bit line is provided for the cell. The bit line is in electrical contact with the gates of the transistor at a pair of bit line contact regions. Both such bit line contact regions are disposed entirely within the isolated region of the cell. With such an arrangement a DRAM cell is provided having a relatively occupies a relatively small amount of surface area of the semiconductor body.

摘要翻译： DRAM单元设置在半导体本体的电隔离区域中。 电池包括设置在沟槽中的存储电容器。 电容器完全设置在半导体本体的隔离区域内。 电池包括设置在隔离区域中的晶体管。 晶体管有一对门。 提供字线用于寻址单元。 字线具有到晶体管的电接触区域。 字线接触区域完全设置在半导体本体的隔离区域内。 晶体管有一个有源区。 有源区域有源极，漏极和沟道区域。 有源区域完全设置在半导体本体的隔离区域内。 为单元提供位线。 位线在一对位线接触区域与晶体管的栅极电接触。 两个这样的位线接触区域完全设置在电池的隔离区域内。 通过这样的布置，提供了DRAM单元，其具有相对占据半导体本体的较小量的表面积。

公开(公告)号：US06319787B1

公开(公告)日：2001-11-20

申请号：US09107980

申请日：1998-06-30

申请人： Gerhard Enders ,  Matthias Ilg ,  Dietrich Widmann

发明人： Gerhard Enders ,  Matthias Ilg ,  Dietrich Widmann

IPC分类号： H01L2120

CPC分类号： H01L27/10861 ,  H01L27/10829

摘要： A trench capacitor having a substrate with a trench extending therein with a nested, e.g., concentric, conductive regions disposed within the trench. A dielectric material is disposed within the substrate. The dielectric material has portions thereof disposed between the concentric conductive regions to dielectrically electrically separate one of the conductive regions from another one of the conductive regions. The dielectrically separated conductive regions provide a pair of electrodes for the capacitor. Selected ones of the concentric conductive regions are electrically connected to provide one of the electrodes for the capacitor. The substrate has a conductive region therein and one of the concentric conductive regions providing one of the electrodes is electrically connected to the conductive region in the substrate. One of the concentric conductive regions is electrically connected to a conductive region in the substrate through a bottom portion of the trench.

摘要翻译： 一种沟槽式电容器，其具有在其中延伸有沟槽的衬底，其具有设置在沟槽内的嵌套的，例如同心的导电区域。 电介质材料设置在衬底内。 电介质材料具有设置在同心导电区域之间的部分，以将导电区域中的一个与另一个导电区域电介质电分离。 介电分离的导电区域为电容器提供一对电极。 选择的同心导电区域被电连接以提供用于电容器的电极之一。 衬底在其中具有导电区域，并且提供电极之一的同心导电区域中的一个电连接到衬底中的导电区域。 一个同心导电区域通过沟槽的底部电连接到衬底中的导电区域。

公开(公告)号：US20070040202A1

公开(公告)日：2007-02-22

申请号：US11206306

申请日：2005-08-18

申请人： Gerhard Enders ,  Marc Strasser ,  Peter Voigt ,  Bjorn Fischer

发明人： Gerhard Enders ,  Marc Strasser ,  Peter Voigt ,  Bjorn Fischer

IPC分类号： H01L29/94 ,  H01L21/8242

CPC分类号： H01L27/10876 ,  H01L27/10861

摘要： In a semiconductor memory including an array of memory cells, each memory cell includes a trench capacitor, the trench capacitor including an inner electrode, an outer electrode and a dielectric layer disposed between the inner electrode and the outer electrode, and a selection transistor, the selection transistor including a first source/drain area, a second source/drain area and a channel region disposed between the first source/drain area and the second source/drain area in a recess, the trench capacitor and the selection transistor of each memory cell are disposed side by side, the first source/drain area of the selection transistor being electrically connected to the inner electrode of the trench capacitor, the recess in which the channel region of the selection transistor is formed being located self aligned between the trench capacitor of the memory cell and the trench capacitor of an adjacent memory cell.

摘要翻译： 在包括存储单元阵列的半导体存储器中，每个存储单元包括沟槽电容器，所述沟槽电容器包括内电极，外电极和设置在内电极和外电极之间的电介质层，以及选择晶体管， 选择晶体管，其包括第一源极/漏极区域，第二源极/漏极区域和设置在凹部中的第一源极/漏极区域和第二源极/漏极区域之间的沟道区域，每个存储器单元的沟槽电容器和选择晶体管 并排配置，选择晶体管的第一源极/漏极区域电连接到沟槽电容器的内部电极，形成选择晶体管的沟道区域的凹槽位于沟槽电容器的沟槽电容器之间， 存储单元和相邻存储单元的沟槽电容器。

公开(公告)号：US07081392B2

公开(公告)日：2006-07-25

申请号：US10897403

申请日：2004-07-23

申请人： Gerhard Enders ,  Peter Voigt

发明人： Gerhard Enders ,  Peter Voigt

IPC分类号： H01L21/336

CPC分类号： H01L29/6659 ,  H01L29/4966 ,  H01L29/66492 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7833

摘要： A method for fabricating a gate structure of a FET, having: (a) deposition and patterning of a sacrificial layer sequence on a semiconductor substrate and uncovering of a gate section; (b) implantation of a channel doping into the gate section; (c) deposition and patterning of spacers at the sidewalls of the sacrificial layer sequence with the formation of a gate section that is not covered by the spacers; (d) introduction of a mask material into the gate section that is not covered by the spacers; (e) removal of the spacers selectively with respect to the sacrificial layer sequence and mask material); (f) implantation of a halo doping in regions uncovered by the removed spacers; (g) removal of the mask material; (h) formation of a gate on the gate section; and (j) removal of the sacrificial layer sequence selectively with respect to the gate.

摘要翻译： 一种用于制造FET的栅极结构的方法，具有：（a）在半导体衬底上沉积和图案化牺牲层序列并露出栅极部分; （b）将沟道掺杂注入到栅极部分中; （c）在牺牲层序列的侧壁处沉积和图案化间隔物，形成未被间隔物覆盖的栅极部分; （d）将掩模材料引入未被间隔物覆盖的栅极部分; （e）相对于牺牲层序列和掩模材料选择性去除间隔物）; （f）在被去除的间隔物覆盖的区域内注入晕圈; （g）去除掩模材料; （h）在栅极部分上形成栅极; 和（j）相对于栅极选择性地去除牺牲层序列。

公开(公告)号：US07009263B2

公开(公告)日：2006-03-07

申请号：US10830675

申请日：2004-04-23

申请人： Gerhard Enders ,  Bjoern Fischer ,  Helmut Schneider ,  Peter Voigt

发明人： Gerhard Enders ,  Bjoern Fischer ,  Helmut Schneider ,  Peter Voigt

IPC分类号： H01L29/76

CPC分类号： H01L29/0649 ,  H01L29/1033

摘要： A field-effect transistor includes a semiconductor substrate, a source region formed in the semiconductor substrate, a drain region formed in the semiconductor substrate, a channel region formed in the semiconductor substrate, wherein the source region is connected to a source terminal electrode and the drain region is connected to a drain terminal electrode, wherein the channel region comprises a first narrow width channel region and a second narrow width channel region connected in parallel regarding the source terminal electrode and the drain terminal electrode, and wherein the first narrow width channel region and/or the second narrow width channel region comprise lateral edges narrowing the width of the narrow width channel region is such a way that a channel formation in the narrow width channel region is influenced by a mutually influencing effect of the lateral edges, and a gate electrode arranged above the first and second narrow width channel regions.

摘要翻译： 场效应晶体管包括半导体衬底，形成在半导体衬底中的源极区域，形成在半导体衬底中的漏极区域，形成在半导体衬底中的沟道区域，其中源极区域连接到源极端子电极， 漏极区域连接到漏极端子电极，其中沟道区域包括关于源极端子电极和漏极端子电极并联连接的第一窄宽度沟道区域和第二窄度沟道区域，并且其中第一窄宽度沟道区域 和/或第二窄宽度沟道区域包括使窄宽度沟道区域的宽度变窄的横向边缘，使得窄宽度沟道区域中的沟道形成受到横向边缘的相互影响的影响， 电极，布置在第一和第二窄宽度通道区域的上方。

公开(公告)号：US09159400B2

公开(公告)日：2015-10-13

申请号：US13422697

申请日：2012-03-16

申请人： Richard Ferrant ,  Gerhard Enders ,  Carlos Mazure

发明人： Richard Ferrant ,  Gerhard Enders ,  Carlos Mazure

IPC分类号： G11C7/06 ,  G11C11/4091 ,  G11C11/4097

CPC分类号： G11C11/4091 ,  G11C7/065 ,  G11C11/4097

摘要： A semiconductor memory having bit lines and wordlines crossing each other, a memory cell array formed by memory cells arranged in rows and columns on crossover points of the bit lines and wordlines, and sense amplifier banks arranged on opposite sides of the memory cell array. Each sense amplifier bank has staggered sense amplifiers connected to a bit line according to an interleaved arrangement whereby bit lines alternate in the direction of the wordlines between bit lines coupled to different sense amplifiers. This results in interconnect spaces parallel to the bit lines. Also, each sense amplifier bank includes a local column decoder for selecting a sense amplifier and which is staggered with the sense amplifiers and coupled to the sense amplifier by an output line running in an available interconnect space parallel to the bit lines.

摘要翻译： 具有彼此交叉的位线和字线的半导体存储器，由位线和字线的交叉点上以列和列排列的存储单元形成的存储单元阵列以及布置在存储单元阵列的相对侧上的读出放大器组。 每个读出放大器组具有根据交错布置连接到位线的交错读出放大器，由此位线在耦合到不同读出放大器的位线之间的字线方向上交替。 这导致互连空间与位线平行。 此外，每个读出放大器组包括本地列解码器，用于选择读出放大器，并与读出放大器交错，并通过在平行于位线的可用互连空间中运行的输出线耦合到读出放大器。

公开(公告)号：US20100090264A1

公开(公告)日：2010-04-15

申请号：US12249060

申请日：2008-10-10

申请人： Hans-Peter Moll ,  Gouri Sankar Kar ,  Martin Popp ,  Lars Heineck ,  Peter Lahnor ,  Arnd Scholz ,  Stefan Jakschik ,  Wolfgang Roesner ,  Gerhard Enders ,  Werner Graf ,  Peter Baars ,  Klaus Muemmler ,  Bernd Hintze ,  Andrei Josiek

发明人： Hans-Peter Moll ,  Gouri Sankar Kar ,  Martin Popp ,  Lars Heineck ,  Peter Lahnor ,  Arnd Scholz ,  Stefan Jakschik ,  Wolfgang Roesner ,  Gerhard Enders ,  Werner Graf ,  Peter Baars ,  Klaus Muemmler ,  Bernd Hintze ,  Andrei Josiek

IPC分类号： H01L27/108 ,  H01L21/02

CPC分类号： H01L27/10891 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885

摘要： One embodiment relates to an integrated circuit formed on a semiconductor body having interconnect between source/drain regions of a first and second transistor. The interconnect includes a metal body arranged underneath the surface of the semiconductor body. A contact element establishes electrical contact between the metal body and the source/drain regions of the first and second transistor. The contact element extends along a connecting path between the source/drain regions of the first and second transistors. Other methods, devices, and systems are also disclosed.

摘要翻译： 一个实施例涉及形成在半导体主体上的集成电路，其具有在第一和第二晶体管的源/漏区之间的互连。 互连件包括布置在半导体本体表面下方的金属体。 接触元件建立金属体与第一和第二晶体管的源/漏区之间的电接触。 接触元件沿着第一和第二晶体管的源极/漏极区域之间的连接路径延伸。 还公开了其它方法，装置和系统。