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    MULTI-DIE DRAM BANKS ARRANGEMENT AND WIRING
    4.
    发明申请
    MULTI-DIE DRAM BANKS ARRANGEMENT AND WIRING 有权
    多模式DRAM银行安排和布线

    公开(公告)号：US20130229848A1

    公开(公告)日：2013-09-05

    申请号：US13885225

    申请日：2011-12-07

    申请人： Thomas Vogelsang

    发明人： Thomas Vogelsang

    IPC分类号： G11C5/06

    CPC分类号： G11C11/4093 ,  G11C5/025 ,  G11C5/06 ,  G11C5/063 ,  G11C8/12 ,  G11C11/4082

    摘要： A memory die for use in a multi-die stack having at least one other die. The memory die includes a plurality of contacts arranged in a field and configured to interface to the other dies of the multi-die stack. A first subset of the buffer lines of a number of buffer lines are connected to respective contacts in the field. The memory die also includes a number of buffers and cross-bar lines. The buffers are coupled between respective signal lines and respective buffer lines. The cross-bar lines interconnect respective pairs of buffer lines in a second subset of the buffer lines that is distinct from the first subset of the buffer lines.

    摘要翻译： 一种用于具有至少一个其它管芯的多管芯堆叠中的存储管芯。 存储器管芯包括布置在场中并被配置为与多管芯堆叠的其它管芯接合的多个触点。 多个缓冲线的缓冲线的第一子集连接到现场的各个触点。 存储器管芯还包括多个缓冲器和横条线。 缓冲器耦合在相应的信号线和相应的缓冲线之间。 跨条线将与缓冲线的第一子集不同的缓冲线的第二子集中的各对缓冲线相互连接。

    MEMORY METHODS AND SYSTEMS WITH ADIABATIC SWITCHING
    5.
    发明申请
    MEMORY METHODS AND SYSTEMS WITH ADIABATIC SWITCHING 有权
    具有自适应切换的记忆方法和系统

    公开(公告)号：US20130114353A1

    公开(公告)日：2013-05-09

    申请号：US13703339

    申请日：2011-08-22

    申请人： Thomas Vogelsang ,  Brent Haukness

    发明人： Thomas Vogelsang ,  Brent Haukness

    IPC分类号： G11C5/14 ,  G11C7/08 ,  G11C7/00

    CPC分类号： G11C5/147 ,  G11C7/00 ,  G11C7/08 ,  G11C7/12 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094

    摘要： A memory system includes wordlines and pairs of complementary bitlines that provide access to memory storage elements. Capacitive and resistive loads associated with wordlines and bitlines are driven relatively slowly between voltage levels to reduce peak current, and thus power dissipation. Power dissipation is further reduced by charging complementary bitlines at substantially different rates.

    摘要翻译： 存储器系统包括提供对存储器存储元件的访问的字线和互补位线对。 与字线和位线相关的电容和电阻负载在电压电平之间相对较慢地驱动，以降低峰值电流，从而降低功耗。 通过以基本不同的速率充电补充位线来进一步降低功耗。

    DRAM SENSE AMPLIFIER THAT SUPPORTS LOW MEMORY-CELL CAPACITANCE
    6.
    发明申请
    DRAM SENSE AMPLIFIER THAT SUPPORTS LOW MEMORY-CELL CAPACITANCE 有权
    DRAM感应放大器，支持低存储容量

    公开(公告)号：US20120230134A1

    公开(公告)日：2012-09-13

    申请号：US13500617

    申请日：2010-11-19

    申请人： Thomas Vogelsang ,  Gary B. Bronner

    发明人： Thomas Vogelsang ,  Gary B. Bronner

    IPC分类号： G11C7/06 ,  H01L21/3213

    CPC分类号： G11C11/4091 ,  G11C7/065 ,  G11C7/08 ,  G11C11/4094 ,  G11C11/4096 ,  H01L27/10873 ,  H01L27/10897

    摘要： The disclosed embodiments provide a sense amplifier for a dynamic random-access memory (DRAM). This sense amplifier includes a bit line to be coupled to a cell to be sensed in the DRAM, and a complement bit line which carries a complement of a signal on the bit line. The sense amplifier also includes a p-type field-effect transistor (PFET) pair comprising cross-coupled PFETs that selectively couple either the bit line or the complement bit line to a high bit-line voltage. The sense amplifier additionally includes an n-type field effect transistor (NFET) pair comprising cross-coupled NFETs that selectively couple either the bit line or the complement bit line to ground. This NFET pair is lightly doped to provide a low threshold-voltage mismatch between NFETs in the NFET pair. In one variation, the gate material for the NFETs is selected to have a work function that compensates for a negative threshold voltage in the NFETs which results from the light substrate doping. In another variation, the sense amplifier additionally includes a cross-coupled pair of latching NFETs. These latching NFETs are normally doped and are configured to latch the voltage on the bit line after the lightly doped NFETs finish sensing the voltage on the bit line.

    摘要翻译： 所公开的实施例提供用于动态随机存取存储器（DRAM）的读出放大器。 该读出放大器包括要耦合到要在DRAM中感测的单元的位线以及在位线上承载信号的补码的补码位线。 读出放大器还包括p型场效应晶体管（PFET）对，其包括选择性地将位线或补码位线耦合到高位线电压的交叉耦合PFET。 读出放大器另外包括n型场效应晶体管（NFET）对，其包括交叉耦合NFET，其选择性地将位线或补码位线耦合到地。 该NFET对被轻掺杂以在NFET对中的NFET之间提供低阈值电压失配。 在一个实施例中，用于NFET的栅极材料被选择为具有补偿由于衬底掺杂导致的NFET中的负阈值电压的功函数。 在另一变型中，读出放大器另外包括交叉耦合的一对锁存NFET。 这些锁存NFET通常是掺杂的，并且被配置为在轻掺杂NFET完成感测位线上的电压之后锁存位线上的电压。

    BIT-REPLACEMENT TECHNIQUE FOR DRAM ERROR CORRECTION
    7.
    发明申请
    BIT-REPLACEMENT TECHNIQUE FOR DRAM ERROR CORRECTION 审中-公开
    用于DRAM错误校正的位替换技术

    公开(公告)号：US20120221902A1

    公开(公告)日：2012-08-30

    申请号：US13505449

    申请日：2010-11-10

    申请人： Frederick A. Ware ,  Ely Tsern ,  Thomas Vogelsang

    发明人： Frederick A. Ware ,  Ely Tsern ,  Thomas Vogelsang

    IPC分类号： G06F11/20

    CPC分类号： G11C29/50016 ,  G06F11/1064 ,  G11C11/401 ,  G11C29/808

    摘要： The disclosed embodiments provide a dynamic memory device, comprising a set of dynamic memory cells and a set of replacement dynamic memory cells. The set of replacement dynamic memory cells includes data cells which contain replacement data bits for predetermined faulty cells in the set of dynamic memory cells, and address cells which contain address bits identifying the faulty cells, wherein each data cell is associated with a group of address cells that identify an associated faulty cell in the set of dynamic memory cells. The dynamic memory device also includes a remapping circuit, which remaps a faulty cell in the set of dynamic memory cells to an associated replacement cell in the set of replacement cells.

    摘要翻译： 所公开的实施例提供了一种动态存储器设备，其包括一组动态存储器单元和一组替换动态存储器单元。 替换动态存储器单元的集合包括包含用于动态存储器单元组中的预定故障单元的替换数据位的数据单元，以及包含标识故障单元的地址位的地址单元，其中每个数据单元与一组地址相关联 识别动态存储器单元组中相关联的故障单元的单元。 动态存储设备还包括重新映射电路，其将该组动态存储器单元中的故障单元重新映射到该替换单元组中的相关联的替换单元。

    METHOD FOR SELF-TEST AND SELF-REPAIR IN A MULTI-CHIP PACKAGE ENVIRONMENT
    8.
    发明申请
    METHOD FOR SELF-TEST AND SELF-REPAIR IN A MULTI-CHIP PACKAGE ENVIRONMENT 有权
    多芯片封装环境中自检和自我修复的方法

    公开(公告)号：US20090063916A1

    公开(公告)日：2009-03-05

    申请号：US11846482

    申请日：2007-08-28

    申请人： Thomas Vogelsang

    发明人： Thomas Vogelsang

    IPC分类号： G11C29/00

    CPC分类号： G11C29/46 ,  G11C5/04 ,  G11C29/4401 ,  G11C29/48 ,  G11C2029/0401

    摘要： A method and apparatus for operating a component including a memory device. The method includes receiving a plurality of commands and determining if a set of the plurality of commands matches a predefined pattern of commands configured to place the memory device into a test mode. Upon determining that the set of the plurality of commands matches the predefined plurality of commands, the memory device is placed in the test mode.

    摘要翻译： 一种用于操作包括存储器件的部件的方法和装置。 所述方法包括接收多个命令并确定所述多个命令的一组是否匹配配置成将所述存储器件置于测试模式中的预定义命令模式。 在确定多个命令的集合与预定义的多个命令匹配时，存储器件被置于测试模式中。

    Fuse resistance read-out circuit
    9.
    发明授权
    Fuse resistance read-out circuit 有权
    保险丝读出电路

    公开(公告)号：US07333383B2

    公开(公告)日：2008-02-19

    申请号：US11210055

    申请日：2005-08-23

    申请人： Thomas Vogelsang

    发明人： Thomas Vogelsang

    IPC分类号： G11C17/18

    CPC分类号： G11C17/18 ,  G11C29/02 ,  G11C29/027 ,  G11C29/50008

    摘要： Methods and apparatus for a more precise readout of fuse resistance than a conventional binary readout are provided. For some embodiments, a digital readout of fuse resistance may be obtained by selectively altering an effective reference resistance to which the fuse resistance is compared. For some embodiments, a direct analog readout may be obtained in addition to, or instead of, a digital resistance readout.

    摘要翻译： 提供了比常规二进制读数更精确地读取熔丝电阻的方法和装置。 对于一些实施例，可以通过选择性地改变比较熔丝电阻的有效参考电阻来获得熔丝电阻的数字读出。 对于一些实施例，除了数字电阻读出之外或代替数字电阻读出，可以获得直接模拟读出。

    Low equalized sense-amp for twin cell DRAMs
    10.
    发明申请
    Low equalized sense-amp for twin cell DRAMs 失效
    双电池DRAM的低均衡感测放大器

    公开(公告)号：US20070070754A1

    公开(公告)日：2007-03-29

    申请号：US11241592

    申请日：2005-09-29

    申请人： Thomas Vogelsang

    发明人： Thomas Vogelsang

    IPC分类号： G11C7/02

    CPC分类号： G11C7/12 ,  G11C11/4094 ,  G11C2211/4013

    摘要： Embodiments of the invention provide a method and apparatus for accessing a twin cell memory device. In one embodiment, a twin memory cell is accessed using a first bitline and a second bitline. The method includes precharging the first bitline and the second bitline to a low voltage. A wordline voltage is asserted to access the twin memory cell. A voltage difference between the first and second bitline is created by a data value and a complement of the data value stored in the twin memory cell, and the voltage difference is sensed.

    摘要翻译： 本发明的实施例提供一种用于访问双胞细胞存储器件的方法和装置。 在一个实施例中，使用第一位线和第二位线访问双存储器单元。 该方法包括将第一位线和第二位线预充电到低电压。 断言字线电压以访问双存储单元。 通过存储在双存储单元中的数据值和数据值的补码产生第一位线和第二位线之间的电压差，并且检测电压差。