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    Selective etching processes of SiO2 , Ti and In2 O3 thin films for FeRAM device applications
    1.
    发明授权
    Selective etching processes of SiO2 , Ti and In2 O3 thin films for FeRAM device applications 失效
    用于FeRAM器件应用的SiO2，Ti和In2 O3薄膜的选择性蚀刻工艺

    公开(公告)号：US07364665B2

    公开(公告)日：2008-04-29

    申请号：US10970885

    申请日：2004-10-21

    申请人： Tingkai Li ,  Bruce D. Ulrich ,  David R. Evans ,  Sheng Teng Hsu

    发明人： Tingkai Li ,  Bruce D. Ulrich ,  David R. Evans ,  Sheng Teng Hsu

    IPC分类号： B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00

    CPC分类号： H01L29/6684 ,  C23F4/00 ,  H01L21/28291 ,  H01L21/31116 ,  H01L21/32136

    摘要： A method of selectively etching a three-layer structure consisting of SiO2, In2O3, and titanium, includes etching the SiO2, stopping at the titanium layer, using C3F8 in a range of between about 10 sccm to 30 sccm; argon in a range of between about 20 sccm to 40 sccm, using an RF source in a range of between about 1000 watts to 3000 watts and an RF bias in a range of between about 400 watts to 800 watts at a pressure in a range of between about 2 mtorr to 6 mtorr; and etching the titanium, stopping at the In2O3 layer, using BCl in a range of between about 10 sccm to 50 sccm; chlorine in a range of between about 40 sccm to 80 sccm, a Tcp in a range of between about 200 watts to 500 watts at an RF bias in a range of between about 100 watts to 200 watts at a pressure in a range of between about 4 mtorr to 8 mtorr.

    摘要翻译： 选择性地蚀刻由SiO 2，In 2 O 3 N 3和Ti构成的三层结构的方法包括蚀刻SiO 2 ，在钛层上停止，使用C 3 3 F 8 N在约10sccm至30sccm之间; 在约20sccm至40sccm的范围内的氩气，使用在约1000瓦特至3000瓦特之间的范围内的RF源和在约400瓦特至800瓦特范围内的RF偏压， 约2mtorr至6mtorr; 并且使用在约10sccm至50sccm之间的范围内的BCl蚀刻钛，停止在In 2 N 3 O 3层处; 在约40sccm至80sccm的范围内的氯，在约200瓦特至200瓦特之间的RF偏压下在约200瓦特至500瓦特之间的范围内的T cp < 在约4mtorr至8mtorr的范围内的压力。

    MOCVD selective deposition of c-axis oriented Pb5Ge3O11 thin films on high-k gate oxides
    2.
    发明授权
    MOCVD selective deposition of c-axis oriented Pb5Ge3O11 thin films on high-k gate oxides 失效
    在高k栅极氧化物上的c轴取向Pb5Ge3O11薄膜的MOCVD选择性沉积

    公开(公告)号：US06794198B1

    公开(公告)日：2004-09-21

    申请号：US10606057

    申请日：2003-06-25

    申请人： Tingkai Li ,  Sheng Teng Hsu ,  David R. Evans ,  Bruce D. Ulrich

    发明人： Tingkai Li ,  Sheng Teng Hsu ,  David R. Evans ,  Bruce D. Ulrich

    IPC分类号： H01L2100

    CPC分类号： H01L21/31691 ,  C23C16/0209 ,  C23C16/40 ,  C23C16/56 ,  H01L21/31604

    摘要： A method of forming a PGO thin film on a high-k dielectric includes preparing a silicon substrate, including forming a high-k gate oxide layer thereon; patterning the high-k gate oxide; annealing the substrate in a first annealing step; placing the substrate in a MOCVD chamber; depositing a PGO thin film by injecting a PGO precursor into the MOCVD chamber; and annealing the structure having a PGO thin film on a high-k gate oxide in a second annealing step.

    摘要翻译： 在高k电介质上形成PGO薄膜的方法包括制备硅衬底，包括在其上形成高k栅极氧化物层; 图案化高k栅极氧化物; 在第一退火步骤中退火衬底; 将基板放置在MOCVD室中; 通过将PGO前体注入到MOCVD室中来沉积PGO薄膜; 以及在第二退火步骤中在高k栅极氧化物上退火具有PGO薄膜的结构。

    Method of etching a SiN/Ir/TaN or SiN/Ir/Ti stack using an aluminum hard mask
    3.
    发明授权
    Method of etching a SiN/Ir/TaN or SiN/Ir/Ti stack using an aluminum hard mask 失效
    使用铝硬掩​​模蚀刻SiN / Ir / TaN或SiN / Ir / Ti叠层的方法

    公开(公告)号：US06951825B2

    公开(公告)日：2005-10-04

    申请号：US10391294

    申请日：2003-03-17

    申请人： Tingkai Li ,  Bruce D. Ulrich ,  David R. Evans ,  Sheng Teng Hsu

    发明人： Tingkai Li ,  Bruce D. Ulrich ,  David R. Evans ,  Sheng Teng Hsu

    IPC分类号： H01L21/3065 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/788 ,  H01L29/792 ,  H01L21/302

    CPC分类号： H01L21/32136 ,  H01L21/31116 ,  H01L21/32139 ,  H01L28/65

    摘要： A method of etching includes preparing a substrate; depositing a first etch stop layer; forming an iridium bottom electrode layer; depositing a SiN layer; depositing and patterning an aluminum hard mask; etching a non-patterned SiN layer with a SiN selective etchant, stopping at the level of the iridium bottom electrode layer; etching the first etch stop layer with a second selective etchant; depositing an oxide layer and CMP the oxide layer to the level of the remaining SiN layer; wet etching the SiN layer to form a trench; depositing a layer of ferroelectric material in the trench formed by removal of the SiN layer; depositing a layer of high-k oxide; and completing the device, including metallization.

    摘要翻译： 蚀刻方法包括准备基板; 沉积第一蚀刻停止层; 形成铱底电极层; 沉积SiN层; 沉积和图案化铝硬掩模; 用SiN选择性蚀刻剂蚀刻未图案化的SiN层，停止在铱底部电极层的水平面上; 用第二选择性蚀刻剂蚀刻第一蚀刻停止层; 将氧化物层沉积并将所述氧化物层CMP沉积到剩余SiN层的水平; 湿式蚀刻SiN层以形成沟槽; 在通过去除SiN层形成的沟槽中沉积一层铁电材料; 沉积一层高K氧化物; 并完成设备，包括金属化。

    Silicon nanostructures and fabrication thereof
    5.
    发明申请
    Silicon nanostructures and fabrication thereof 审中-公开
    硅纳米结构及其制造

    公开(公告)号：US20080166878A1

    公开(公告)日：2008-07-10

    申请号：US11651242

    申请日：2007-01-08

    申请人： Tingkai Li ,  Bruce D. Ulrich ,  Jer-Shen Maa ,  Sheng Teng Hsu

    发明人： Tingkai Li ,  Bruce D. Ulrich ,  Jer-Shen Maa ,  Sheng Teng Hsu

    IPC分类号： H01L21/306

    CPC分类号： H01L21/31111 ,  B81C1/00111 ,  H01L21/3065 ,  H01L21/31122

    摘要： A method of fabricating silicon nanostructures includes preparing a silicon wafer as a substrate; forming an oxide layer hardmask directly on the silicon substrate; patterning and etching the oxide hardmask; wet etching the silicon wafer to remove oxide to reduce the size of the oxide hardmask and to form nanostructure elements; and dry etching, in one or more steps, the silicon wafer using the oxide hardmask to form a desired nanostructure having substantially parallel vertical sidewalls thereon.

    摘要翻译： 制造硅纳米结构的方法包括制备硅晶片作为基底; 在硅衬底上直接形成氧化层硬掩模; 图案化和蚀刻氧化物硬掩模; 湿蚀刻硅晶片以除去氧化物以减小氧化物硬掩模的尺寸并形成纳米结构元件; 以及使用氧化物硬掩模在一个或多个步骤中干蚀刻硅晶片以形成其上具有基本上平行的垂直侧壁的所需纳米结构。

    Selective etching processes of silicon nitride and indium oxide thin films for FeRAM device applications
    6.
    发明授权
    Selective etching processes of silicon nitride and indium oxide thin films for FeRAM device applications 失效
    用于FeRAM器件应用的氮化硅和氧化铟薄膜的选择性蚀刻工艺

    公开(公告)号：US07338907B2

    公开(公告)日：2008-03-04

    申请号：US10958537

    申请日：2004-10-04

    申请人： Tingkai Li ,  Sheng Teng Hsu ,  Bruce D. Ulrich ,  Mark A. Burgholzer ,  Ray A. Hill

    发明人： Tingkai Li ,  Sheng Teng Hsu ,  Bruce D. Ulrich ,  Mark A. Burgholzer ,  Ray A. Hill

    IPC分类号： H01L21/311

    CPC分类号： H01L21/31116 ,  H01L29/6684 ,  H01L29/78391

    摘要： A dry etch process is described for selectively etching silicon nitride from conductive oxide material for use in a semiconductor fabrication process. Adding an oxidant in the etch gas mixture could increase the etch rate for the silicon nitride while reducing the etch rate for the conductive oxide, resulting in improving etch selectivity. The disclosed selective etch process is well suited for ferroelectric memory device fabrication using conductive oxide/ferroelectric interface having silicon nitride as the encapsulated material for the ferroelectric.

    摘要翻译： 描述了一种干蚀刻工艺，用于从用于半导体制造工艺的导电氧化物材料中选择性地蚀刻氮化硅。 在蚀刻气体混合物中添加氧化剂可以增加氮化硅的蚀刻速率，同时降低导电氧化物的蚀刻速率，从而提高蚀刻选择性。 所公开的选择性蚀刻工艺非常适合于使用具有氮化硅作为铁电体的封装材料的导电氧化物/铁电界面的铁电存储器件制造。

    Integration processes for fabricating a conductive metal oxide gate ferroelectric memory transistor
    9.
    发明授权
    Integration processes for fabricating a conductive metal oxide gate ferroelectric memory transistor 失效
    用于制造导电金属氧化物栅极铁电存储晶体管的集成工艺

    公开(公告)号：US07329548B2

    公开(公告)日：2008-02-12

    申请号：US11215521

    申请日：2005-08-30

    申请人： Tingkai Li ,  Sheng Teng Hsu ,  Bruce D. Ulrich

    发明人： Tingkai Li ,  Sheng Teng Hsu ,  Bruce D. Ulrich

    IPC分类号： H01L21/00 ,  H01L21/338 ,  H01L21/8242

    CPC分类号： H01L21/28291 ,  H01L29/66583 ,  H01L29/78

    摘要： A method of fabricating a conductive metal oxide gate ferroelectric memory transistor includes forming an oxide layer a substrate and removing the oxide layer in a gate area; depositing a conductive metal oxide layer on the oxide layer and on the exposed gate area; depositing a titanium layer on the metal oxide layer; patterning and etching the titanium layer and the metal oxide layer to remove the titanium layer and the metal oxide layer from the substrate except in the gate area; depositing, patterning and etching an oxide layer to form a gate trench; depositing and etching a barrier insulator layer to form a sidewall barrier in the gate trench; removing the titanium layer from the gate area; depositing, smoothing and annealing a ferroelectric layer in the gate trench; depositing, patterning and etching a top electrode; and completing the conductive metal oxide gate ferroelectric memory transistor.

    摘要翻译： 一种制造导电金属氧化物栅极铁电存储晶体管的方法，包括：在衬底上形成氧化物层并去除栅极区域中的氧化物层; 在氧化物层和暴露的栅极区上沉积导电金属氧化物层; 在所述金属氧化物层上沉积钛层; 图案化和蚀刻钛层和金属氧化物层以除去栅极区域之外的基板以除去钛层和金属氧化物层; 沉积，图案化和蚀刻氧化物层以形成栅极沟槽; 沉积和蚀刻阻挡绝缘体层以在栅极沟槽中形成侧壁势垒; 从栅极区域去除钛层; 沉积，平滑和退火栅极沟槽中的铁电层; 沉积，图案化和蚀刻顶部电极; 并完成导电金属氧化物栅极铁电存储晶体管。

    Ultra-shallow metal oxide surface channel MOS transistor
    10.
    发明授权
    Ultra-shallow metal oxide surface channel MOS transistor 失效
    超浅金属氧化物表面沟道MOS晶体管

    公开(公告)号：US07256465B2

    公开(公告)日：2007-08-14

    申请号：US10761704

    申请日：2004-01-21

    申请人： Tingkai Li ,  Sheng Teng Hsu ,  Bruce D. Ulrich

    发明人： Tingkai Li ,  Sheng Teng Hsu ,  Bruce D. Ulrich

    IPC分类号： H01L21/336 ,  H01L29/94

    CPC分类号： H01L29/66545 ,  H01L29/1054 ,  H01L29/26 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/7833

    摘要： An ultra-shallow surface channel MOS transistor and method for fabricating the same have been provided. The method comprises: forming CMOS source and drain regions, and an intervening well region; depositing a surface channel on the surface overlying the well region; forming a high-k dielectric overlying the surface channel; and, forming a gate electrode overlying the high-k dielectric. Typically, the surface channel is a metal oxide, and may be one of the following materials: indium oxide (In2O3), ZnO, RuO, ITO, or LaX-1SrXCoO3. In some aspects, the method further comprises: depositing a placeholder material overlying the surface channel; and, etching the placeholder material to form a gate region overlying the surface channel. In one aspect, the high-k dielectric is deposited prior to the deposition of the placeholder material. Alternately, the high-k dielectric is deposited following the etching of the placeholder material.

    摘要翻译： 提供了一种超浅表面沟道MOS晶体管及其制造方法。 该方法包括：形成CMOS源极和漏极区域以及中间阱区域; 在覆盖所述阱区域的表面上沉积表面通道; 形成覆盖表面通道的高k电介质; 并形成覆盖高k电介质的栅电极。 通常，表面通道是金属氧化物，并且可以是以下材料之一：氧化铟（In 2 O 3），ZnO，RuO，ITO或LaX-1SrXCoO 3。 在一些方面，所述方法还包括：沉积覆盖所述表面通道的占位符材料; 并且蚀刻占位符材料以形成覆盖表面通道的栅极区域。 在一个方面，高k电介质沉积在占位符材料的沉积之前。 或者，在占位符材料的蚀刻之后沉积高k电介质。