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    Methods of forming a local interconnect method of fabricating integrated circuitry comprising an SRAM cell having a local interconnect and having circuitry peripheral to the SRAM cell and method of forming contact plugs
    1.
    发明授权
    Methods of forming a local interconnect method of fabricating integrated circuitry comprising an SRAM cell having a local interconnect and having circuitry peripheral to the SRAM cell and method of forming contact plugs 失效
    形成集成电路的局部互连方法的方法，该集成电路包括具有局部互连并且具有SRAM单元的外围电路的SRAM单元和形成接触插塞的方法

    公开(公告)号：US06333254B1

    公开(公告)日：2001-12-25

    申请号：US09737919

    申请日：2000-12-14

    申请人： Todd R. Abbott ,  Michael P. Violette ,  Charles H. Dennison

    发明人： Todd R. Abbott ,  Michael P. Violette ,  Charles H. Dennison

    IPC分类号： H01L214763

    CPC分类号： H01L27/11 ,  H01L21/76877 ,  H01L21/76895 ,  H01L27/1104

    摘要： In one implementation, a substrate is provided which has at least two nodes to be electrically connected. A first conductivity type semiconductive material is formed over and in electrical connection with one of the nodes. A conductive diffusion barrier material is formed over and in electrical connection with the first conductivity type semiconductive material. A second conductivity type semiconductive material is formed over and in electrical connection with the first conductivity type semiconductive material through the conductive diffusion barrier material, and over and in electrical connection with another of the nodes. The first conductivity type semiconductive material, the conductive diffusion barrier material and the second conductivity type semiconductive material are formed into a local interconnect electrically connecting the one node and the another node. Local interconnects fabricated by this and other methods are also contemplated. The invention includes in one implementation a method of forming contact plugs.

    摘要翻译： 在一个实施方案中，提供了具有至少两个要电连接的节点的基板。 第一导电类型的半导体材料形成在节点之一上并与其中的一个节点电连接。 导电扩散阻挡材料形成在第一导电类型半导体材料之上并与第一导电类型的半导体材料电连接。 第二导电类型半导体材料通过导电扩散阻挡材料形成在第一导电类型半导体材料之上并与电连接，并且与另一节点电连接。 第一导电型半导体材料，导电扩散阻挡材料和第二导电类型半导体材料形成为电连接一个节点和另一个节点的局部互连。 也可以设想通过该方法和其它方法制造的局部互连。 本发明在一个实施方案中包括形成接触塞的方法。

    METHOD OF FORMING A LOCAL INTERCONNECT, METHOD OF FABRICATING INTEGRATED CIRCUITRY COMPRISING AN SRAM CELL HAVING A LOCAL INTERCONNECT AND HAVING CIRCUITRY PERIPHERAL TO THE SRAM CELL, AND METHOD OF FORMING CONTACT PLUGS
    2.
    发明授权
    METHOD OF FORMING A LOCAL INTERCONNECT, METHOD OF FABRICATING INTEGRATED CIRCUITRY COMPRISING AN SRAM CELL HAVING A LOCAL INTERCONNECT AND HAVING CIRCUITRY PERIPHERAL TO THE SRAM CELL, AND METHOD OF FORMING CONTACT PLUGS 有权
    形成本地互连的方法，将包含具有本地互连的具有电路外围的SRAM单元的集成电路整合到SRAM单元的方法以及形成接触电极的方法

    公开(公告)号：US06380596B1

    公开(公告)日：2002-04-30

    申请号：US09935469

    申请日：2001-08-21

    申请人： Todd R. Abbott ,  Michael P. Violette ,  Charles H. Dennison

    发明人： Todd R. Abbott ,  Michael P. Violette ,  Charles H. Dennison

    IPC分类号： H01L31119

    CPC分类号： H01L27/11 ,  H01L21/76877 ,  H01L21/76895 ,  H01L27/1104

    摘要： In one implementation, a substrate is provided which has at least two nodes to be electrically connected. A first conductivity type semiconductive material is formed over and in electrical connection with one of the nodes. A conductive diffusion barrier material is formed over and in electrical connection with the first conductivity type semiconductive material. A second conductivity type semiconductive material is formed over and in electrical connection with the first conductivity type semiconductive material through the conductive diffusion barrier material, and over and in electrical connection with another of the nodes. The first conductivity type semiconductive material, the conductive diffusion barrier material and the second conductivity type semiconductive material are formed into a local interconnect electrically connecting the one node and the another node. Local interconnects fabricated by this and other methods are also contemplated. The invention includes in one implementation a method of forming contact plugs.

    摘要翻译： 在一个实施方案中，提供了具有至少两个要电连接的节点的基板。 第一导电类型的半导体材料形成在节点之一上并与其中的一个节点电连接。 导电扩散阻挡材料形成在第一导电类型半导体材料之上并与第一导电类型的半导体材料电连接。 第二导电类型半导体材料通过导电扩散阻挡材料形成在第一导电类型半导体材料之上并与电连接，并且与另一节点电连接。 第一导电型半导体材料，导电扩散阻挡材料和第二导电类型半导体材料形成为电连接一个节点和另一个节点的局部互连。 也可以设想通过该方法和其它方法制造的局部互连。 本发明在一个实施方案中包括形成接触塞的方法。

    PHASE CHANGE MEMORY CELL WITH CONSTRICTION STRUCTURE
    7.
    发明申请
    PHASE CHANGE MEMORY CELL WITH CONSTRICTION STRUCTURE 有权
    相位变化记忆体与调制结构

    公开(公告)号：US20090231911A1

    公开(公告)日：2009-09-17

    申请号：US12049056

    申请日：2008-03-14

    申请人： Jun Liu ,  Michael P. Violette

    发明人： Jun Liu ,  Michael P. Violette

    IPC分类号： G11C11/00 ,  H01L47/00 ,  H01L21/00

    CPC分类号： H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1608 ,  H01L45/1675 ,  H01L45/1683

    摘要： Some embodiments include apparatus and methods having a memory cell with a first electrode and a second electrode, and a memory element directly contacting the first and second electrodes. The memory element may include a programmable portion having a material configured to change between multiple phases. The programmable portion may be isolated from the first electrode by a first portion of the memory element and isolated from the second electrode by a second portion of the memory element.

    摘要翻译： 一些实施例包括具有具有第一电极和第二电极的存储单元的设备和方法，以及直接接触第一和第二电极的存储元件。 存储元件可以包括具有被配置为在多个相之间变化的材料的可编程部分。 可编程部分可以通过存储元件的第一部分与第一电极隔离，并且通过存储元件的第二部分与第二电极隔离。

    Semiconductor fuses and semiconductor devices containing the same
    9.
    发明授权
    Semiconductor fuses and semiconductor devices containing the same 失效
    半导体保险丝和含有其的半导体器件

    公开(公告)号：US06927473B2

    公开(公告)日：2005-08-09

    申请号：US10620054

    申请日：2003-07-14

    申请人： Zhongze Wang ,  Michael P. Violette ,  Jigish Trivedi

    发明人： Zhongze Wang ,  Michael P. Violette ,  Jigish Trivedi

    IPC分类号： H01L23/525 ,  H01L29/00

    CPC分类号： H01L21/76888 ,  H01L23/5256 ,  H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Fuses for integrated circuits and semiconductor devices, methods for making and using the same, and semiconductor devices containing the same. The semiconductor fuse contains two conductive layers, an overlying and underlying layer, on an insulating substrate. The underlying layer comprises titanium nitride and the overlying layer comprises tungsten silicide. The semiconductor fuse may be fabricated during manufacture of a local interconnect structure containing the same materials. The fuse, which may be used to program redundant circuitry, is blown by electrical current rather than laser beams, thus allowing the fuse width to be smaller than prior art fuses blown by laser beams. The fuse may also be blown by less electrical current than the current required to blow conventional polysilicon fuses having similar dimensions.

    摘要翻译： 用于集成电路和半导体器件的保险丝，其制造和使用的方法以及包含该保险丝的半导体器件。 半导体熔丝在绝缘基板上包含两层导电层，一层覆盖和下层。 底层包括氮化钛，上覆层包括硅化钨。 半导体保险丝可以在制造包含相同材料的局部互连结构时制造。 可用于编程冗余电路的保险丝由电流而不是激光束吹扫，从而允许熔丝宽度小于由激光束吹制的现有技术的熔丝。 熔断器也可能被吹过比吹出具有相似尺寸的常规多晶硅保险丝所需的电流更小的电流。

    Fuse for use in a semiconductor device, and semiconductor devices including the fuse
    10.
    发明授权
    Fuse for use in a semiconductor device, and semiconductor devices including the fuse 有权

    公开(公告)号：US06495902B2

    公开(公告)日：2002-12-17

    申请号：US09943993

    申请日：2001-08-30

    申请人： Kenneth W. Marr ,  Michael P. Violette

    发明人： Kenneth W. Marr ,  Michael P. Violette

    IPC分类号： H01L2900

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A metal silicide fuse for a semiconductor device. The fuse includes a conductive region positioned adjacent a common well of a first conductivity type, a terminal region positioned adjacent a well of a second conductivity type, and a narrowed region located between the terminal region and the conductive region and positioned adjacent a boundary between the two wells. Upon applying at least a programming current to the fuse, the fuse “blows” at the narrowed region. The diode or diodes between wells of different conductivity types wells and the Schottky diode or diodes between the remaining portions of the fuse and wells adjacent thereto control the flow of current through the remainder of the fuse and through the associated wells of the semiconductor device. When the fuse has been “blown,” the diodes and Schottky diodes prevent current of a normal operating voltage from flowing through the wells of the semiconductor device.