公开(公告)号：US5691938A

公开(公告)日：1997-11-25

申请号：US237226

申请日：1994-05-03

申请人： Tom Dang-Hsing Yiu ,  Fuchia Shone ,  Tien-Ler Lin ,  Ling Chen

发明人： Tom Dang-Hsing Yiu ,  Fuchia Shone ,  Tien-Ler Lin ,  Ling Chen

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  G11C16/06

CPC分类号： H01L27/11519 ,  G11C16/0491 ,  H01L27/115 ,  H01L27/11521

摘要： An improved contactless EPROM array, EPROM cell design, and method for fabricating the same is based on a unique drain-source-drain configuration, in which a single source diffusion is shared by two columns of transistors. An elongated first drain diffusion region, an elongated source diffusion region, and an elongated second drain diffusion region, are formed in a semi-conductor substrate along essentially parallel lines. Field oxide regions are grown on opposite sides of the first and second drain diffusion regions. Floating gates and control gate wordlines are formed orthogonal to the drain-source-drain structure to establish two columns of storage cells having a shared source region. The shared source region is coupled through a bottom block select transistor to a virtual ground terminal. Each drain diffusion region is-coupled through a top block select transistor to global bitline. The cell structure uses two metal global bitlines which extend essentially parallel to the drain, source and drain diffusion regions, and a virtual ground conductor which couples a plurality of columns of transistors to a virtual ground terminal through a horizontal conductor, such as a buried diffusion line.

摘要翻译： 改进的非接触式EPROM阵列，EPROM单元设计及其制造方法基于唯一的漏极 - 源极 - 漏极配置，其中单个源极扩散由两列晶体管共享。 沿着基本上平行的线，在半导体衬底中形成细长的第一漏极扩散区域，细长源极扩散区域和细长的第二漏极扩散区域。 场氧化物区域在第一和第二漏极扩散区域的相对侧上生长。 浮置栅极和控制栅极字线与漏极 - 源极 - 漏极结构正交形成，以建立具有共享源极区域的两列存储单元。 共享源极区域通过底部块选择晶体管耦合到虚拟接地端子。 每个漏极扩散区域通过顶部块选择晶体管耦合到全局位线。 电池结构使用两个基本平行于漏极，源极和漏极扩散区域延伸的金属全局位线，以及通过水平导体（例如埋入扩散）将多个晶体管列耦合到虚拟接地端子的虚拟接地导体 线。

公开(公告)号：US5633185A

公开(公告)日：1997-05-27

申请号：US390775

申请日：1995-02-17

申请人： Tom Dang-Hsing Yiu ,  Fuchia Shone ,  Tien-Ler Lin ,  Ling Chen

发明人： Tom Dang-Hsing Yiu ,  Fuchia Shone ,  Tien-Ler Lin ,  Ling Chen

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11519 ,  G11C16/0491 ,  H01L27/115 ,  H01L27/11521

摘要： An improved contactless EPROM array, EPROM cell design, and method for fabricating the same is based on a unique drain-source-drain configuration, in which a single source diffusion is shared by two columns of transistors. An elongated first drain diffusion region, an elongated source diffusion region, and an elongated second drain diffusion region, are formed in a semi-conductor substrate along essentially parallel lines. Field oxide regions are grown on opposite sides of the first and second drain diffusion regions. Floating gates and control gate wordlines are formed orthogonal to the drain-source-drain structure to establish two columns of storage cells having a shared source region. The shared source region is coupled through a bottom block select transistor to a virtual ground terminal. Each drain diffusion region is coupled through a top block select transistor to global bitline. The cell structure uses two metal global bitlines which extend essentially parallel to the drain, source and drain diffusion regions, and a virtual ground conductor which couples a plurality of columns of transistors to a virtual ground terminal through a horizontal conductor, such as a buried diffusion line.

摘要翻译： 改进的非接触式EPROM阵列，EPROM单元设计及其制造方法基于唯一的漏极 - 源极 - 漏极配置，其中单个源极扩散由两列晶体管共享。 沿着基本上平行的线，在半导体衬底中形成细长的第一漏极扩散区域，细长源极扩散区域和细长的第二漏极扩散区域。 场氧化物区域在第一和第二漏极扩散区域的相对侧上生长。 浮置栅极和控制栅极字线与漏极 - 源极 - 漏极结构正交形成，以建立具有共享源极区域的两列存储单元。 共享源极区域通过底部块选择晶体管耦合到虚拟接地端子。 每个漏极扩散区域通过顶部块选择晶体管耦合到全局位线。 电池结构使用两个基本平行于漏极，源极和漏极扩散区域延伸的金属全局位线，以及通过水平导体（例如埋入扩散）将多个晶体管列耦合到虚拟接地端子的虚拟接地导体 线。

公开(公告)号：US5821909A

公开(公告)日：1998-10-13

申请号：US700587

申请日：1996-08-14

申请人： Tom Dang-Hsing Yiu ,  Ray L. Wan ,  Ling-Wen Hsiao ,  Tien-Ler Lin ,  Fuchia Shone

发明人： Tom Dang-Hsing Yiu ,  Ray L. Wan ,  Ling-Wen Hsiao ,  Tien-Ler Lin ,  Fuchia Shone

IPC分类号： G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/24 ,  G11C16/02

CPC分类号： G11C16/12 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24

摘要： A circuit for speeding up the pre-programming of floating gate storage transistors such as FLASH EPROMS, and particularly speeding up the pre-programming of a block or array of floating gate storage transistors includes a controllable voltage source that supplies gate programming potential across the control gate and source of the FLASH EPROM transistor cells to be programmed. A control circuit is provided that controls the voltage source to vary the gate programming potential during a programming interval as a function of time in order to decrease the time required for a given amount of charge movement to program the selected floating gate transistors. The wordline voltages are varied, while the source voltage is held constant. By starting at a lower wordline voltage, and increasing during the programming interval to a high wordline voltage, the programming speed is increased, and the high final turn-on threshold voltage for the programmed floating gate storage transistors is achieved. In addition, in order to speed up pre-programming, a programming potential is applied to four wordlines in parallel during a single programming interval. Further, the load on cells being programmed is adjusted to improve programming speed.

公开(公告)号：US6166956A

公开(公告)日：2000-12-26

申请号：US303153

申请日：1999-04-30

申请人： Tom Dang-Hsing Yiu ,  Ray L. Wan ,  Ling-Wen Hsiao ,  Tien-Ler Lin ,  Fuchia Shone

发明人： Tom Dang-Hsing Yiu ,  Ray L. Wan ,  Ling-Wen Hsiao ,  Tien-Ler Lin ,  Fuchia Shone

IPC分类号： G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/24 ,  G11C7/00

CPC分类号： G11C16/12 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24

摘要： A circuit for speeding up the pre-programming of floating gate storage transistors such as FLASH EPROMS, and particularly speeding up the pre-programming of a block or array of floating gate storage transistors includes a controllable voltage source that supplies gate programming potential across the control gate and source of the FLASH EPROM transistor cells to be programmed. A control circuit is provided that controls the voltage source to vary the gate programming potential during a programming interval as a function of time in order to decrease the time required for a given amount of charge movement to program the selected floating gate transistors. The wordline voltages are varied, while the source voltage is held constant. By starting at a lower wordline voltage, and increasing during the programming interval to a high wordline voltage, the programming speed is increased, and the high final turn-on threshold voltage for the programmed floating gate storage transistors is achieved. In addition, in order to speed up pre-programming, a programming potential is applied to four wordlines in parallel during a single programming interval. Further, the load on cells being programmed is adjusted to improve programming speed.

摘要翻译： 用于加速浮动存储晶体管（例如FLASH EPROMS）的预编程的电路，并且特别是加速块或阵列的浮置栅极存储晶体管的预编程包括可控电压源，其提供跨控制的栅极编程电位 要编程的FLASH EPROM晶体管单元的栅极和源极。 提供控制电路，其控制电压源以在编程间隔期间作为时间的函数改变栅极编程电位，以便减少给定量的电荷移动对所选择的浮置栅极晶体管进行编程所需的时间。 字线电压是变化的，而源电压保持恒定。 通过以较低的字线电压开始，并且在编程间隔期间增加到高字线电压，编程速度增加，并且实现了编程浮栅存储晶体管的高最终导通阈值电压。 另外，为了加速预编程，在单个编程间隔期间，编程电位并行应用于四个字线。 此外，调整正在编程的单元上的负载以提高编程速度。

公开(公告)号：US5453391A

公开(公告)日：1995-09-26

申请号：US67519

申请日：1993-05-25

申请人： Tom D. Yiu ,  Fuchia Shone ,  Tien-Ler Lin ,  Ling Chen

发明人： Tom D. Yiu ,  Fuchia Shone ,  Tien-Ler Lin ,  Ling Chen

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11519 ,  G11C16/0491 ,  H01L27/115 ,  H01L27/11521

摘要： An improved contactless EPROM array, EPROM cell design, and method for fabricating the same is based on a unique drain-source-drain configuration, in which a single source diffusion is shared by two columns of transistors. An elongated first drain diffusion region, an elongated source diffusion region, and an elongated second drain diffusion region, are formed in a semi-conductor substrate along essentially parallel lines. Field oxide regions are grown on opposite sides of the first and second drain diffusion regions. Floating gates and control gate wordlines are formed orthogonal to the drain-source-drain structure to establish two columns of storage cells having a shared source region. The shared source region is coupled through a bottom block select transistor to a virtual ground terminal. Each drain diffusion region is coupled through a top block select transistor to global bitline. The cell structure uses two metal global bitlines which extend essentially parallel to the drain, source and drain diffusion regions, and a virtual ground conductor which couples a plurality of columns of transistors to a virtual ground terminal through a horizontal conductor, such as a buried diffusion line.

摘要翻译： 改进的非接触式EPROM阵列，EPROM单元设计及其制造方法基于唯一的漏极 - 源极 - 漏极配置，其中单个源极扩散由两列晶体管共享。 沿着基本上平行的线，在半导体衬底中形成细长的第一漏极扩散区域，细长源极扩散区域和细长的第二漏极扩散区域。 场氧化物区域在第一和第二漏极扩散区域的相对侧上生长。 浮置栅极和控制栅极字线与漏极 - 源极 - 漏极结构正交形成，以建立具有共享源极区域的两列存储单元。 共享源极区域通过底部块选择晶体管耦合到虚拟接地端子。 每个漏极扩散区域通过顶部块选择晶体管耦合到全局位线。 电池结构使用两个基本平行于漏极，源极和漏极扩散区域延伸的金属全局位线，以及通过水平导体（例如埋入扩散）将多个晶体管列耦合到虚拟接地端子的虚拟接地导体 线。

公开(公告)号：US5399891A

公开(公告)日：1995-03-21

申请号：US187118

申请日：1994-01-25

申请人： Tom D. H. Yiu ,  Fuchia Shone ,  Tien-Ler Lin ,  Ling Chen

发明人： Tom D. H. Yiu ,  Fuchia Shone ,  Tien-Ler Lin ,  Ling Chen

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/68 ,  H01L29/78

CPC分类号： H01L27/11519 ,  G11C16/0491 ,  H01L27/115 ,  H01L27/11521

摘要： Novel contactless FLASH EPROM cell and array designs, and methods for fabricating the same is based on a unique drain-source-drain configuration, in which a single source diffusion is shared by two columns of transistors. An elongated first drain diffusion region, an elongated source diffusion region, and an elongated second drain diffusion region, are formed in a semi-conductor substrate along essentially parallel lines. Field oxide regions are grown on opposite sides of the first and second drain diffusion regions. Floating gates and control gate wordlines are formed orthogonal to the drain-source-drain structure to establish two columns of storage cells having a shared source region. The shared source region is coupled through a bottom block select transistor to a virtual ground terminal. Each drain diffusion region is coupled through a top block select transistor to global bitline. The cell structure uses two metal global bitlines which extend essentially parallel to the drain, source and drain diffusion regions, and a virtual ground conductor which couples a plurality of columns of transistors to a virtual ground terminal through a horizontal conductor, such as a buried diffusion line.

摘要翻译： 新型非接触式FLASH EPROM单元和阵列设计及其制造方法基于独特的漏 - 源 - 漏配置，其中单个源扩散由两列晶体管共享。 沿着基本上平行的线，在半导体衬底中形成细长的第一漏极扩散区域，细长源极扩散区域和细长的第二漏极扩散区域。 场氧化物区域在第一和第二漏极扩散区域的相对侧上生长。 浮置栅极和控制栅极字线与漏极 - 源极 - 漏极结构正交形成，以建立具有共享源极区域的两列存储单元。 共享源极区域通过底部块选择晶体管耦合到虚拟接地端子。 每个漏极扩散区域通过顶部块选择晶体管耦合到全局位线。 电池结构使用两个基本平行于漏极，源极和漏极扩散区域延伸的金属全局位线，以及通过水平导体（例如埋入扩散）将多个晶体管列耦合到虚拟接地端子的虚拟接地导体 线。

公开(公告)号：US5778440A

公开(公告)日：1998-07-07

申请号：US596380

申请日：1996-02-16

申请人： Tom Dang-Hsing Yiu ,  Ray-Lin Wan ,  Yao-Wu Cheng ,  Chung-Hsiung Hung ,  Fuchia Shone

发明人： Tom Dang-Hsing Yiu ,  Ray-Lin Wan ,  Yao-Wu Cheng ,  Chung-Hsiung Hung ,  Fuchia Shone

IPC分类号： G11C16/04 ,  G11C16/32 ,  G11C16/34 ,  G06F13/00 ,  G11C16/06

CPC分类号： G11C16/0491 ,  G08G1/017 ,  G11C16/32 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521

摘要： A floating gate memory with a protocol which terminates a program load cycle upon detecting a predetermined address and/or data pattern, providing positive indication of the end of the load cycle, and eliminating the requirement for a long pulse in a controlled signal. Command logic executes a process to store a block of data in response to a sequence of addresses and data segments received at the input/output circuitry, and detects the last segment in a block of data in response to a pattern including at least one of the addresses and data segments received at the input/output circuitry. One pattern includes consecutive matching addresses. Pattern match logic included in the command logic is coupled to the input/output circuitry and stores addresses in the sequence and compares them with a next address to indicate a matching address. Alternatively, the pattern includes both matching addresses and data segments with corresponding comparator circuitry. Alternatively, the pattern comprises a command address which is outside the address field of the memory array. The command address may include all or only a high order segment of the actual data address. The floating gate memory includes a state machine which automatically programs and verifies programming of the block of data after the last segment of the block is detected, and may comprise a flash memory or electrically erasable programmable read only memory (EEPROM).

摘要翻译： PCT No.PCT / US95 / 06762 Sec。 371日期1996年2月16日 102（e）日期1996年2月16日PCT 1995年5月26日提交具有协议的浮动门存储器，其在检测到预定地址和/或数据模式时终止程序加载周期，提供负载循环结束的正向指示， 并消除了对受控信号中的长脉冲的要求。 响应于在输入/输出电路处接收的地址和数据段的序列，命令逻辑执行存储数据块的过程，并响应于包括至少一个的模式来检测数据块中的最后一个段 在输入/输出电路处接收的地址和数据段。 一种模式包括连续的匹配地址。 包括在命令逻辑中的模式匹配逻辑被耦合到输入/输出电路，并且存储序列中的地址，并将它们与下一个地址进行比较以指示匹配的地址。 或者，该模式包括具有对应的比较器电路的匹配地址和数据段。 或者，该模式包括在存储器阵列的地址字段之外的命令地址。 命令地址可以包括实际数据地址的全部或仅有高阶段。 浮动门存储器包括在检测到块的最后段之后自动编程和验证数据块的编程的状态机，并且可以包括闪速存储器或电可擦除可编程只读存储器（EEPROM）。

公开(公告)号：US5745410A

公开(公告)日：1998-04-28

申请号：US619485

申请日：1996-03-21

申请人： Tom Dang-Hsing Yiu ,  Fuchia Shone ,  I-Long Lee ,  Chia-Shing Chen ,  Hun-Song Chen ,  Yuan-Chang Liu ,  Tzeng-Huei Shiau ,  Kuen-Long Chang ,  Ray-Lin Wan

发明人： Tom Dang-Hsing Yiu ,  Fuchia Shone ,  I-Long Lee ,  Chia-Shing Chen ,  Hun-Song Chen ,  Yuan-Chang Liu ,  Tzeng-Huei Shiau ,  Kuen-Long Chang ,  Ray-Lin Wan

IPC分类号： G11C11/40

CPC分类号： G11C11/40

摘要： A floating gate memory device which includes control circuits to generate a repair pulse to repair over-erased cells so they may be repaired block-by-block. This invention includes repairing the cells by applying a repair pulse to the cell's bit line while maintaining the word line voltage above ground. In a different embodiment, the word line voltage is maintained at two different voltage levels above ground. In the first stage, the word line voltage is maintained between approximately 0.1 volts and 0.2 volts for approximately 100 ms while the repair pulse is applied. In the second stage, the word line voltage is maintained between approximately 0.4 volts and 0.5 volts for approximately 100 ms while the repair pulse is applied.

摘要翻译： PCT No.PCT / US95 / 15051 Sec。 371日期1996年3月21日 102（e）1996年3月21日PCT 1995年11月17日PCT PCT。 第WO97 / 19452号公报 日期1997年5月29日一种浮动栅极存储器件，其包括产生修复脉冲以修复过擦除的单元的控制电路，使得它们可以逐块修复。 本发明包括通过在维持字线电压高于地面的同时将修复脉冲施加到单元的位线来修复单元。 在不同的实施例中，字线电压保持在地面以上两个不同的电压电平。 在第一阶段，当施加修复脉冲时，字线电压保持在大约0.1伏和0.2伏之间大约100毫秒。 在第二阶段，当施加修复脉冲时，字线电压保持在大约0.4伏和0.5伏之间大约100毫秒。

公开(公告)号：US5563823A

公开(公告)日：1996-10-08

申请号：US393243

申请日：1995-02-23

申请人： Tom D. Yiu ,  Ray L. Wan ,  Ling-Wen Hsiao ,  Tien-Ler Lin ,  Fuchia Shone

发明人： Tom D. Yiu ,  Ray L. Wan ,  Ling-Wen Hsiao ,  Tien-Ler Lin ,  Fuchia Shone

IPC分类号： G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/24 ,  G11C7/00

CPC分类号： G11C16/12 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24

摘要： A circuit for speeding up the pre-programming of floating gate storage transistors such as FLASH EPROMS, and particularly speeding up the pre-programming of a block or array of floating gate storage transistors includes a controllable voltage source that supplies gate programming potential across the control gate and source of the FLASH EPROM transistor cells to be programmed. A control circuit is provided that controls the voltage source to vary the gate programming potential during a programming interval as a function of time in order to decrease the time required for a given amount of charge movement to program the selected floating gate transistors. The wordline voltages are varied, while the source voltage is held constant. By starting at a lower wordline voltage, and increasing during the programming interval to a high wordline voltage, the programming speed is increased, and the high final turn-on threshold voltage for the programmed floating gate storage transistors is achieved. In addition, in order to speed up pre-programming, a programming potential is applied to four wordlines in parallel during a single programming interval. Further, the load on cells being programmed is adjusted to improve programming speed.

摘要翻译： 用于加速浮动存储晶体管（例如FLASH EPROMS）的预编程的电路，并且特别是加速块或阵列的浮置栅极存储晶体管的预编程包括可控电压源，其提供跨控制的栅极编程电位 要编程的FLASH EPROM晶体管单元的栅极和源极。 提供控制电路，其控制电压源以在编程间隔期间作为时间的函数改变栅极编程电位，以便减少给定量的电荷移动对所选择的浮置栅极晶体管进行编程所需的时间。 字线电压是变化的，而源电压保持恒定。 通过以较低的字线电压开始，并且在编程间隔期间增加到高字线电压，编程速度增加，并且实现了编程浮栅存储晶体管的高最终导通阈值电压。 另外，为了加速预编程，在单个编程间隔期间，编程电位并行应用于四个字线。 此外，调整正在编程的单元上的负载以提高编程速度。

公开(公告)号：US5539688A

公开(公告)日：1996-07-23

申请号：US444313

申请日：1995-05-18

申请人： Tom D. Yiu ,  Ray L. Wan ,  Ling-Wen Hsiao ,  Tien-Ler Lin ,  Fuchia Shone

发明人： Tom D. Yiu ,  Ray L. Wan ,  Ling-Wen Hsiao ,  Tien-Ler Lin ,  Fuchia Shone

IPC分类号： G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/24 ,  G11C16/06

CPC分类号： G11C16/12 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24

摘要： A circuit for speeding up the pre-programming of floating gate storage transistors such as FLASH EPROMS, and particularly speeding up the pre-programming of a block or array of floating gate storage transistors includes a controllable voltage source that supplies gate programming potential across the control gate and source of the FLASH EPROM transistor cells to be programmed. A control circuit is provided that controls the voltage source to vary the gate programming potential during a programming interval as a function of time in order to decrease the time required for a given amount of charge movement to program the selected floating gate transistors. The wordline voltages are varied, while the source voltage is held constant. By starting at a lower wordline voltage, and increasing during the programming interval to a high wordline voltage, the programming speed is increased, and the high final turn-on threshold voltage for the programmed floating gate storage transistors is achieved. In addition, in order to speed up pre-programming, a programming potential is applied to four wordlines in parallel during a single programming interval. Further, the load on cells being programmed is adjusted to improve programming speed.

摘要翻译： 用于加速浮动存储晶体管（例如FLASH EPROMS）的预编程的电路，并且特别是加速块或阵列的浮置栅极存储晶体管的预编程包括可控电压源，其提供跨控制的栅极编程电位 要编程的FLASH EPROM晶体管单元的栅极和源极。 提供控制电路，其控制电压源以在编程间隔期间作为时间的函数改变栅极编程电位，以便减少给定量的电荷移动对所选择的浮置栅极晶体管进行编程所需的时间。 字线电压是变化的，而源电压保持恒定。 通过以较低的字线电压开始，并且在编程间隔期间增加到高字线电压，编程速度增加，并且实现了编程浮栅存储晶体管的高最终导通阈值电压。 另外，为了加速预编程，在单个编程间隔期间，编程电位并行应用于四个字线。 此外，调整正在编程的单元上的负载以提高编程速度。