公开(公告)号：US5691938A

公开(公告)日：1997-11-25

申请号：US237226

申请日：1994-05-03

申请人： Tom Dang-Hsing Yiu ,  Fuchia Shone ,  Tien-Ler Lin ,  Ling Chen

发明人： Tom Dang-Hsing Yiu ,  Fuchia Shone ,  Tien-Ler Lin ,  Ling Chen

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  G11C16/06

CPC分类号： H01L27/11519 ,  G11C16/0491 ,  H01L27/115 ,  H01L27/11521

摘要： An improved contactless EPROM array, EPROM cell design, and method for fabricating the same is based on a unique drain-source-drain configuration, in which a single source diffusion is shared by two columns of transistors. An elongated first drain diffusion region, an elongated source diffusion region, and an elongated second drain diffusion region, are formed in a semi-conductor substrate along essentially parallel lines. Field oxide regions are grown on opposite sides of the first and second drain diffusion regions. Floating gates and control gate wordlines are formed orthogonal to the drain-source-drain structure to establish two columns of storage cells having a shared source region. The shared source region is coupled through a bottom block select transistor to a virtual ground terminal. Each drain diffusion region is-coupled through a top block select transistor to global bitline. The cell structure uses two metal global bitlines which extend essentially parallel to the drain, source and drain diffusion regions, and a virtual ground conductor which couples a plurality of columns of transistors to a virtual ground terminal through a horizontal conductor, such as a buried diffusion line.

摘要翻译： 改进的非接触式EPROM阵列，EPROM单元设计及其制造方法基于唯一的漏极 - 源极 - 漏极配置，其中单个源极扩散由两列晶体管共享。 沿着基本上平行的线，在半导体衬底中形成细长的第一漏极扩散区域，细长源极扩散区域和细长的第二漏极扩散区域。 场氧化物区域在第一和第二漏极扩散区域的相对侧上生长。 浮置栅极和控制栅极字线与漏极 - 源极 - 漏极结构正交形成，以建立具有共享源极区域的两列存储单元。 共享源极区域通过底部块选择晶体管耦合到虚拟接地端子。 每个漏极扩散区域通过顶部块选择晶体管耦合到全局位线。 电池结构使用两个基本平行于漏极，源极和漏极扩散区域延伸的金属全局位线，以及通过水平导体（例如埋入扩散）将多个晶体管列耦合到虚拟接地端子的虚拟接地导体 线。

公开(公告)号：US5633185A

公开(公告)日：1997-05-27

申请号：US390775

申请日：1995-02-17

申请人： Tom Dang-Hsing Yiu ,  Fuchia Shone ,  Tien-Ler Lin ,  Ling Chen

发明人： Tom Dang-Hsing Yiu ,  Fuchia Shone ,  Tien-Ler Lin ,  Ling Chen

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11519 ,  G11C16/0491 ,  H01L27/115 ,  H01L27/11521

摘要： An improved contactless EPROM array, EPROM cell design, and method for fabricating the same is based on a unique drain-source-drain configuration, in which a single source diffusion is shared by two columns of transistors. An elongated first drain diffusion region, an elongated source diffusion region, and an elongated second drain diffusion region, are formed in a semi-conductor substrate along essentially parallel lines. Field oxide regions are grown on opposite sides of the first and second drain diffusion regions. Floating gates and control gate wordlines are formed orthogonal to the drain-source-drain structure to establish two columns of storage cells having a shared source region. The shared source region is coupled through a bottom block select transistor to a virtual ground terminal. Each drain diffusion region is coupled through a top block select transistor to global bitline. The cell structure uses two metal global bitlines which extend essentially parallel to the drain, source and drain diffusion regions, and a virtual ground conductor which couples a plurality of columns of transistors to a virtual ground terminal through a horizontal conductor, such as a buried diffusion line.

摘要翻译： 改进的非接触式EPROM阵列，EPROM单元设计及其制造方法基于唯一的漏极 - 源极 - 漏极配置，其中单个源极扩散由两列晶体管共享。 沿着基本上平行的线，在半导体衬底中形成细长的第一漏极扩散区域，细长源极扩散区域和细长的第二漏极扩散区域。 场氧化物区域在第一和第二漏极扩散区域的相对侧上生长。 浮置栅极和控制栅极字线与漏极 - 源极 - 漏极结构正交形成，以建立具有共享源极区域的两列存储单元。 共享源极区域通过底部块选择晶体管耦合到虚拟接地端子。 每个漏极扩散区域通过顶部块选择晶体管耦合到全局位线。 电池结构使用两个基本平行于漏极，源极和漏极扩散区域延伸的金属全局位线，以及通过水平导体（例如埋入扩散）将多个晶体管列耦合到虚拟接地端子的虚拟接地导体 线。

公开(公告)号：US5821909A

公开(公告)日：1998-10-13

申请号：US700587

申请日：1996-08-14

申请人： Tom Dang-Hsing Yiu ,  Ray L. Wan ,  Ling-Wen Hsiao ,  Tien-Ler Lin ,  Fuchia Shone

发明人： Tom Dang-Hsing Yiu ,  Ray L. Wan ,  Ling-Wen Hsiao ,  Tien-Ler Lin ,  Fuchia Shone

IPC分类号： G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/24 ,  G11C16/02

CPC分类号： G11C16/12 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24

摘要： A circuit for speeding up the pre-programming of floating gate storage transistors such as FLASH EPROMS, and particularly speeding up the pre-programming of a block or array of floating gate storage transistors includes a controllable voltage source that supplies gate programming potential across the control gate and source of the FLASH EPROM transistor cells to be programmed. A control circuit is provided that controls the voltage source to vary the gate programming potential during a programming interval as a function of time in order to decrease the time required for a given amount of charge movement to program the selected floating gate transistors. The wordline voltages are varied, while the source voltage is held constant. By starting at a lower wordline voltage, and increasing during the programming interval to a high wordline voltage, the programming speed is increased, and the high final turn-on threshold voltage for the programmed floating gate storage transistors is achieved. In addition, in order to speed up pre-programming, a programming potential is applied to four wordlines in parallel during a single programming interval. Further, the load on cells being programmed is adjusted to improve programming speed.

公开(公告)号：US6166956A

公开(公告)日：2000-12-26

申请号：US303153

申请日：1999-04-30

申请人： Tom Dang-Hsing Yiu ,  Ray L. Wan ,  Ling-Wen Hsiao ,  Tien-Ler Lin ,  Fuchia Shone

发明人： Tom Dang-Hsing Yiu ,  Ray L. Wan ,  Ling-Wen Hsiao ,  Tien-Ler Lin ,  Fuchia Shone

IPC分类号： G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/24 ,  G11C7/00

CPC分类号： G11C16/12 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24

摘要： A circuit for speeding up the pre-programming of floating gate storage transistors such as FLASH EPROMS, and particularly speeding up the pre-programming of a block or array of floating gate storage transistors includes a controllable voltage source that supplies gate programming potential across the control gate and source of the FLASH EPROM transistor cells to be programmed. A control circuit is provided that controls the voltage source to vary the gate programming potential during a programming interval as a function of time in order to decrease the time required for a given amount of charge movement to program the selected floating gate transistors. The wordline voltages are varied, while the source voltage is held constant. By starting at a lower wordline voltage, and increasing during the programming interval to a high wordline voltage, the programming speed is increased, and the high final turn-on threshold voltage for the programmed floating gate storage transistors is achieved. In addition, in order to speed up pre-programming, a programming potential is applied to four wordlines in parallel during a single programming interval. Further, the load on cells being programmed is adjusted to improve programming speed.

摘要翻译： 用于加速浮动存储晶体管（例如FLASH EPROMS）的预编程的电路，并且特别是加速块或阵列的浮置栅极存储晶体管的预编程包括可控电压源，其提供跨控制的栅极编程电位 要编程的FLASH EPROM晶体管单元的栅极和源极。 提供控制电路，其控制电压源以在编程间隔期间作为时间的函数改变栅极编程电位，以便减少给定量的电荷移动对所选择的浮置栅极晶体管进行编程所需的时间。 字线电压是变化的，而源电压保持恒定。 通过以较低的字线电压开始，并且在编程间隔期间增加到高字线电压，编程速度增加，并且实现了编程浮栅存储晶体管的高最终导通阈值电压。 另外，为了加速预编程，在单个编程间隔期间，编程电位并行应用于四个字线。 此外，调整正在编程的单元上的负载以提高编程速度。

公开(公告)号：US5453391A

公开(公告)日：1995-09-26

申请号：US67519

申请日：1993-05-25

申请人： Tom D. Yiu ,  Fuchia Shone ,  Tien-Ler Lin ,  Ling Chen

发明人： Tom D. Yiu ,  Fuchia Shone ,  Tien-Ler Lin ,  Ling Chen

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11519 ,  G11C16/0491 ,  H01L27/115 ,  H01L27/11521

摘要： An improved contactless EPROM array, EPROM cell design, and method for fabricating the same is based on a unique drain-source-drain configuration, in which a single source diffusion is shared by two columns of transistors. An elongated first drain diffusion region, an elongated source diffusion region, and an elongated second drain diffusion region, are formed in a semi-conductor substrate along essentially parallel lines. Field oxide regions are grown on opposite sides of the first and second drain diffusion regions. Floating gates and control gate wordlines are formed orthogonal to the drain-source-drain structure to establish two columns of storage cells having a shared source region. The shared source region is coupled through a bottom block select transistor to a virtual ground terminal. Each drain diffusion region is coupled through a top block select transistor to global bitline. The cell structure uses two metal global bitlines which extend essentially parallel to the drain, source and drain diffusion regions, and a virtual ground conductor which couples a plurality of columns of transistors to a virtual ground terminal through a horizontal conductor, such as a buried diffusion line.

摘要翻译： 改进的非接触式EPROM阵列，EPROM单元设计及其制造方法基于唯一的漏极 - 源极 - 漏极配置，其中单个源极扩散由两列晶体管共享。 沿着基本上平行的线，在半导体衬底中形成细长的第一漏极扩散区域，细长源极扩散区域和细长的第二漏极扩散区域。 场氧化物区域在第一和第二漏极扩散区域的相对侧上生长。 浮置栅极和控制栅极字线与漏极 - 源极 - 漏极结构正交形成，以建立具有共享源极区域的两列存储单元。 共享源极区域通过底部块选择晶体管耦合到虚拟接地端子。 每个漏极扩散区域通过顶部块选择晶体管耦合到全局位线。 电池结构使用两个基本平行于漏极，源极和漏极扩散区域延伸的金属全局位线，以及通过水平导体（例如埋入扩散）将多个晶体管列耦合到虚拟接地端子的虚拟接地导体 线。

公开(公告)号：US5399891A

公开(公告)日：1995-03-21

申请号：US187118

申请日：1994-01-25

申请人： Tom D. H. Yiu ,  Fuchia Shone ,  Tien-Ler Lin ,  Ling Chen

发明人： Tom D. H. Yiu ,  Fuchia Shone ,  Tien-Ler Lin ,  Ling Chen

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/68 ,  H01L29/78

CPC分类号： H01L27/11519 ,  G11C16/0491 ,  H01L27/115 ,  H01L27/11521

摘要： Novel contactless FLASH EPROM cell and array designs, and methods for fabricating the same is based on a unique drain-source-drain configuration, in which a single source diffusion is shared by two columns of transistors. An elongated first drain diffusion region, an elongated source diffusion region, and an elongated second drain diffusion region, are formed in a semi-conductor substrate along essentially parallel lines. Field oxide regions are grown on opposite sides of the first and second drain diffusion regions. Floating gates and control gate wordlines are formed orthogonal to the drain-source-drain structure to establish two columns of storage cells having a shared source region. The shared source region is coupled through a bottom block select transistor to a virtual ground terminal. Each drain diffusion region is coupled through a top block select transistor to global bitline. The cell structure uses two metal global bitlines which extend essentially parallel to the drain, source and drain diffusion regions, and a virtual ground conductor which couples a plurality of columns of transistors to a virtual ground terminal through a horizontal conductor, such as a buried diffusion line.

摘要翻译： 新型非接触式FLASH EPROM单元和阵列设计及其制造方法基于独特的漏 - 源 - 漏配置，其中单个源扩散由两列晶体管共享。 沿着基本上平行的线，在半导体衬底中形成细长的第一漏极扩散区域，细长源极扩散区域和细长的第二漏极扩散区域。 场氧化物区域在第一和第二漏极扩散区域的相对侧上生长。 浮置栅极和控制栅极字线与漏极 - 源极 - 漏极结构正交形成，以建立具有共享源极区域的两列存储单元。 共享源极区域通过底部块选择晶体管耦合到虚拟接地端子。 每个漏极扩散区域通过顶部块选择晶体管耦合到全局位线。 电池结构使用两个基本平行于漏极，源极和漏极扩散区域延伸的金属全局位线，以及通过水平导体（例如埋入扩散）将多个晶体管列耦合到虚拟接地端子的虚拟接地导体 线。

公开(公告)号：US5818848A

公开(公告)日：1998-10-06

申请号：US770479

申请日：1996-12-20

申请人： Tien-Ler Lin ,  Tom Dang-Hsing Yiu ,  Ray L. Wan ,  Kong-Mou Liou

发明人： Tien-Ler Lin ,  Tom Dang-Hsing Yiu ,  Ray L. Wan ,  Kong-Mou Liou

IPC分类号： G11C17/00 ,  G11C29/00 ,  G11C29/02 ,  G11C29/44 ,  G11C29/48

CPC分类号： G11C29/44 ,  G11C29/48

摘要： An integrated circuit comprises a functional module such as a FLASH memory with automatic program and erase circuits, test circuitry coupled with the functional module which executes a test of the functional module and generates status information as a result of the test, and non-volatile status write circuitry coupled with the test circuitry on the chip. A circuit in the non-volatile status write circuitry is responsive to the test of the functional circuitry to write the status information to the non-volatile memory. A port is provided on the integrated circuit coupled to the non-volatile memory through which the status information stored in the non-volatile memory is accessible in a test read mode to external devices. In a FLASH EPROM embodiment, the IC includes an array of FLASH EPROM memory cells and a port through which data in the array is accessible by external devices. A test set of FLASH EPROM memory cells is provided in the array. Program and erase circuitry, coupled to the array, has a test mode to exercise the program and erase circuitry to generate status information indicating results of the test and test read mode to read out the status information. Non-volatile status write circuitry, is coupled to the program and erase circuitry and the test set, and writes the status information to the test set. The program and erase circuits include retry counts with programmable thresholds for reducing the test times of the devices.

摘要翻译： 集成电路包括诸如具有自动编程和擦除电路的闪存的功能模块，与功能模块耦合的测试电路，其执行功能模块的测试并且作为测试的结果生成状态信息，以及非易失性状态 写入电路与芯片上的测试电路耦合。 非易失性状态写入电路中的电路响应于功能电路的测试以将状态信息写入非易失性存储器。 在与非易失性存储器耦合的集成电路上提供端口，通过该端口，存储在非易失性存储器中的状态信息可以以测试读取模式访问到外部设备。 在FLASH EPROM实施例中，IC包括闪存EPROM存储器单元阵列和阵列中的数据可由外部设备访问的端口。 阵列中提供了一组FLASH EPROM存储单元。 耦合到阵列的编程和擦除电路具有运行程序和擦除电路的测试模式，以产生指示测试结果的状态信息和测试读取模式以读出状态信息。 非易失性状态写入电路耦合到程序和擦除电路和测试仪，并将状态信息写入测试仪。 程序和擦除电路包括具有可编程阈值的重试计数，以减少器件的测试时间。

公开(公告)号：US5691945A

公开(公告)日：1997-11-25

申请号：US605100

申请日：1996-03-01

申请人： Kong-Mou Liou ,  Tom Dang-Hsing Yiu ,  Ray-Lin Wan ,  Yao-Wu Cheng ,  Chun-Hsiung Hung ,  Ting-Chung Hu ,  Tien-Ler Lin

发明人： Kong-Mou Liou ,  Tom Dang-Hsing Yiu ,  Ray-Lin Wan ,  Yao-Wu Cheng ,  Chun-Hsiung Hung ,  Ting-Chung Hu ,  Tien-Ler Lin

IPC分类号： G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C29/00 ,  G11C7/00

CPC分类号： G11C29/76 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12

摘要： A flexible technique for improving yield of manufacturing of high density of memory devices, such as flash EEPROM, involves reconfiguring an integrated circuit memory array having a plurality of sectors selected by an address decoder in response to an N bit field in an address. If defective sectors are detected in the array, it is partitioned to disable defective sectors by configuring a sector decoder to prevent access to the defective sectors while maintaining sequential addressing remaining sectors in the array. The step of partitioning includes configuring the sector decoder to replace a defective sector in one half of the array by another sector in the other half of the array having N-m of the N address bits in common with the defective sector when m is between 1 and N-1.

摘要翻译： PCT No.PCT / US95 / 06990第 371日期1996年3月1日 102（e）1996年3月1日PCT 1995年5月31日PCT PCT。 公开号WO96 / 38845 日期1996年12月5日用于提高高密度存储器件（例如闪存EEPROM）的制造成品率的灵活技术涉及重新配置具有由地址解码器选择的多个扇区的集成电路存储器阵列，以响应于N位字段 一个地址 如果在阵列中检测到有缺陷的扇区，则通过配置扇区解码器以防止对阵列中的剩余扇区的顺序寻址，同时对阵列解码器进行划分以禁用缺陷扇区。 分割步骤包括配置扇区解码器以在阵列的另一半中的另外一个扇区替换阵列的一半中的缺陷扇区，其中，当m在1和N之间时，具有与缺陷扇区相同的N个地址位的Nm -1。

公开(公告)号：US5563822A

公开(公告)日：1996-10-08

申请号：US444315

申请日：1995-05-18

申请人： Tom D. Yiu ,  Ray L. Wan ,  Ling-Wen Hsiao ,  Tien-Ler Lin ,  Fuchia Shone

发明人： Tom D. Yiu ,  Ray L. Wan ,  Ling-Wen Hsiao ,  Tien-Ler Lin ,  Fuchia Shone

IPC分类号： G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/24 ,  G11C13/00

CPC分类号： G11C16/12 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24

摘要： A circuit for speeding up the pre-programming of floating gate storage transistors such as FLASH EPROMS, and particularly speeding up the pre-programming of a block or array of floating gate storage transistors includes a controllable voltage source that supplies gate programming potential across the control gate and source of the FLASH EPROM transistor cells to be programmed. A control circuit is provided that controls the voltage source to vary the gate programming potential during a programming interval as a function of time in order to decrease the time required for a given amount of charge movement to program the selected floating gate transistors. The wordline voltages are varied, while the source voltage is held constant. By starting at a lower wordline voltage, and increasing during the programming interval to a high wordline voltage, the programming speed is increased, and the high final turn-on threshold voltage for the programmed floating gate storage transistors is achieved. In addition, in order to speed up pre-programming, a programming potential is applied to four wordlines in parallel during a single programming interval. Further, the load on cells being programmed is adjusted to improve programming speed.

公开(公告)号：US5563823A

公开(公告)日：1996-10-08

申请号：US393243

申请日：1995-02-23

申请人： Tom D. Yiu ,  Ray L. Wan ,  Ling-Wen Hsiao ,  Tien-Ler Lin ,  Fuchia Shone

发明人： Tom D. Yiu ,  Ray L. Wan ,  Ling-Wen Hsiao ,  Tien-Ler Lin ,  Fuchia Shone

IPC分类号： G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/24 ,  G11C7/00

CPC分类号： G11C16/12 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24

摘要： A circuit for speeding up the pre-programming of floating gate storage transistors such as FLASH EPROMS, and particularly speeding up the pre-programming of a block or array of floating gate storage transistors includes a controllable voltage source that supplies gate programming potential across the control gate and source of the FLASH EPROM transistor cells to be programmed. A control circuit is provided that controls the voltage source to vary the gate programming potential during a programming interval as a function of time in order to decrease the time required for a given amount of charge movement to program the selected floating gate transistors. The wordline voltages are varied, while the source voltage is held constant. By starting at a lower wordline voltage, and increasing during the programming interval to a high wordline voltage, the programming speed is increased, and the high final turn-on threshold voltage for the programmed floating gate storage transistors is achieved. In addition, in order to speed up pre-programming, a programming potential is applied to four wordlines in parallel during a single programming interval. Further, the load on cells being programmed is adjusted to improve programming speed.

摘要翻译： 用于加速浮动存储晶体管（例如FLASH EPROMS）的预编程的电路，并且特别是加速块或阵列的浮置栅极存储晶体管的预编程包括可控电压源，其提供跨控制的栅极编程电位 要编程的FLASH EPROM晶体管单元的栅极和源极。 提供控制电路，其控制电压源以在编程间隔期间作为时间的函数改变栅极编程电位，以便减少给定量的电荷移动对所选择的浮置栅极晶体管进行编程所需的时间。 字线电压是变化的，而源电压保持恒定。 通过以较低的字线电压开始，并且在编程间隔期间增加到高字线电压，编程速度增加，并且实现了编程浮栅存储晶体管的高最终导通阈值电压。 另外，为了加速预编程，在单个编程间隔期间，编程电位并行应用于四个字线。 此外，调整正在编程的单元上的负载以提高编程速度。