公开(公告)号：US5691938A

公开(公告)日：1997-11-25

申请号：US237226

申请日：1994-05-03

申请人： Tom Dang-Hsing Yiu ,  Fuchia Shone ,  Tien-Ler Lin ,  Ling Chen

发明人： Tom Dang-Hsing Yiu ,  Fuchia Shone ,  Tien-Ler Lin ,  Ling Chen

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  G11C16/06

CPC分类号： H01L27/11519 ,  G11C16/0491 ,  H01L27/115 ,  H01L27/11521

摘要： An improved contactless EPROM array, EPROM cell design, and method for fabricating the same is based on a unique drain-source-drain configuration, in which a single source diffusion is shared by two columns of transistors. An elongated first drain diffusion region, an elongated source diffusion region, and an elongated second drain diffusion region, are formed in a semi-conductor substrate along essentially parallel lines. Field oxide regions are grown on opposite sides of the first and second drain diffusion regions. Floating gates and control gate wordlines are formed orthogonal to the drain-source-drain structure to establish two columns of storage cells having a shared source region. The shared source region is coupled through a bottom block select transistor to a virtual ground terminal. Each drain diffusion region is-coupled through a top block select transistor to global bitline. The cell structure uses two metal global bitlines which extend essentially parallel to the drain, source and drain diffusion regions, and a virtual ground conductor which couples a plurality of columns of transistors to a virtual ground terminal through a horizontal conductor, such as a buried diffusion line.

摘要翻译： 改进的非接触式EPROM阵列，EPROM单元设计及其制造方法基于唯一的漏极 - 源极 - 漏极配置，其中单个源极扩散由两列晶体管共享。 沿着基本上平行的线，在半导体衬底中形成细长的第一漏极扩散区域，细长源极扩散区域和细长的第二漏极扩散区域。 场氧化物区域在第一和第二漏极扩散区域的相对侧上生长。 浮置栅极和控制栅极字线与漏极 - 源极 - 漏极结构正交形成，以建立具有共享源极区域的两列存储单元。 共享源极区域通过底部块选择晶体管耦合到虚拟接地端子。 每个漏极扩散区域通过顶部块选择晶体管耦合到全局位线。 电池结构使用两个基本平行于漏极，源极和漏极扩散区域延伸的金属全局位线，以及通过水平导体（例如埋入扩散）将多个晶体管列耦合到虚拟接地端子的虚拟接地导体 线。

公开(公告)号：US5633185A

公开(公告)日：1997-05-27

申请号：US390775

申请日：1995-02-17

申请人： Tom Dang-Hsing Yiu ,  Fuchia Shone ,  Tien-Ler Lin ,  Ling Chen

发明人： Tom Dang-Hsing Yiu ,  Fuchia Shone ,  Tien-Ler Lin ,  Ling Chen

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11519 ,  G11C16/0491 ,  H01L27/115 ,  H01L27/11521

摘要： An improved contactless EPROM array, EPROM cell design, and method for fabricating the same is based on a unique drain-source-drain configuration, in which a single source diffusion is shared by two columns of transistors. An elongated first drain diffusion region, an elongated source diffusion region, and an elongated second drain diffusion region, are formed in a semi-conductor substrate along essentially parallel lines. Field oxide regions are grown on opposite sides of the first and second drain diffusion regions. Floating gates and control gate wordlines are formed orthogonal to the drain-source-drain structure to establish two columns of storage cells having a shared source region. The shared source region is coupled through a bottom block select transistor to a virtual ground terminal. Each drain diffusion region is coupled through a top block select transistor to global bitline. The cell structure uses two metal global bitlines which extend essentially parallel to the drain, source and drain diffusion regions, and a virtual ground conductor which couples a plurality of columns of transistors to a virtual ground terminal through a horizontal conductor, such as a buried diffusion line.

摘要翻译： 改进的非接触式EPROM阵列，EPROM单元设计及其制造方法基于唯一的漏极 - 源极 - 漏极配置，其中单个源极扩散由两列晶体管共享。 沿着基本上平行的线，在半导体衬底中形成细长的第一漏极扩散区域，细长源极扩散区域和细长的第二漏极扩散区域。 场氧化物区域在第一和第二漏极扩散区域的相对侧上生长。 浮置栅极和控制栅极字线与漏极 - 源极 - 漏极结构正交形成，以建立具有共享源极区域的两列存储单元。 共享源极区域通过底部块选择晶体管耦合到虚拟接地端子。 每个漏极扩散区域通过顶部块选择晶体管耦合到全局位线。 电池结构使用两个基本平行于漏极，源极和漏极扩散区域延伸的金属全局位线，以及通过水平导体（例如埋入扩散）将多个晶体管列耦合到虚拟接地端子的虚拟接地导体 线。

公开(公告)号：US5821909A

公开(公告)日：1998-10-13

申请号：US700587

申请日：1996-08-14

申请人： Tom Dang-Hsing Yiu ,  Ray L. Wan ,  Ling-Wen Hsiao ,  Tien-Ler Lin ,  Fuchia Shone

发明人： Tom Dang-Hsing Yiu ,  Ray L. Wan ,  Ling-Wen Hsiao ,  Tien-Ler Lin ,  Fuchia Shone

IPC分类号： G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/24 ,  G11C16/02

CPC分类号： G11C16/12 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24

摘要： A circuit for speeding up the pre-programming of floating gate storage transistors such as FLASH EPROMS, and particularly speeding up the pre-programming of a block or array of floating gate storage transistors includes a controllable voltage source that supplies gate programming potential across the control gate and source of the FLASH EPROM transistor cells to be programmed. A control circuit is provided that controls the voltage source to vary the gate programming potential during a programming interval as a function of time in order to decrease the time required for a given amount of charge movement to program the selected floating gate transistors. The wordline voltages are varied, while the source voltage is held constant. By starting at a lower wordline voltage, and increasing during the programming interval to a high wordline voltage, the programming speed is increased, and the high final turn-on threshold voltage for the programmed floating gate storage transistors is achieved. In addition, in order to speed up pre-programming, a programming potential is applied to four wordlines in parallel during a single programming interval. Further, the load on cells being programmed is adjusted to improve programming speed.

公开(公告)号：US6166956A

公开(公告)日：2000-12-26

申请号：US303153

申请日：1999-04-30

申请人： Tom Dang-Hsing Yiu ,  Ray L. Wan ,  Ling-Wen Hsiao ,  Tien-Ler Lin ,  Fuchia Shone

发明人： Tom Dang-Hsing Yiu ,  Ray L. Wan ,  Ling-Wen Hsiao ,  Tien-Ler Lin ,  Fuchia Shone

IPC分类号： G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/24 ,  G11C7/00

CPC分类号： G11C16/12 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24

摘要： A circuit for speeding up the pre-programming of floating gate storage transistors such as FLASH EPROMS, and particularly speeding up the pre-programming of a block or array of floating gate storage transistors includes a controllable voltage source that supplies gate programming potential across the control gate and source of the FLASH EPROM transistor cells to be programmed. A control circuit is provided that controls the voltage source to vary the gate programming potential during a programming interval as a function of time in order to decrease the time required for a given amount of charge movement to program the selected floating gate transistors. The wordline voltages are varied, while the source voltage is held constant. By starting at a lower wordline voltage, and increasing during the programming interval to a high wordline voltage, the programming speed is increased, and the high final turn-on threshold voltage for the programmed floating gate storage transistors is achieved. In addition, in order to speed up pre-programming, a programming potential is applied to four wordlines in parallel during a single programming interval. Further, the load on cells being programmed is adjusted to improve programming speed.

摘要翻译： 用于加速浮动存储晶体管（例如FLASH EPROMS）的预编程的电路，并且特别是加速块或阵列的浮置栅极存储晶体管的预编程包括可控电压源，其提供跨控制的栅极编程电位 要编程的FLASH EPROM晶体管单元的栅极和源极。 提供控制电路，其控制电压源以在编程间隔期间作为时间的函数改变栅极编程电位，以便减少给定量的电荷移动对所选择的浮置栅极晶体管进行编程所需的时间。 字线电压是变化的，而源电压保持恒定。 通过以较低的字线电压开始，并且在编程间隔期间增加到高字线电压，编程速度增加，并且实现了编程浮栅存储晶体管的高最终导通阈值电压。 另外，为了加速预编程，在单个编程间隔期间，编程电位并行应用于四个字线。 此外，调整正在编程的单元上的负载以提高编程速度。

公开(公告)号：US5818848A

公开(公告)日：1998-10-06

申请号：US770479

申请日：1996-12-20

申请人： Tien-Ler Lin ,  Tom Dang-Hsing Yiu ,  Ray L. Wan ,  Kong-Mou Liou

发明人： Tien-Ler Lin ,  Tom Dang-Hsing Yiu ,  Ray L. Wan ,  Kong-Mou Liou

IPC分类号： G11C17/00 ,  G11C29/00 ,  G11C29/02 ,  G11C29/44 ,  G11C29/48

CPC分类号： G11C29/44 ,  G11C29/48

摘要： An integrated circuit comprises a functional module such as a FLASH memory with automatic program and erase circuits, test circuitry coupled with the functional module which executes a test of the functional module and generates status information as a result of the test, and non-volatile status write circuitry coupled with the test circuitry on the chip. A circuit in the non-volatile status write circuitry is responsive to the test of the functional circuitry to write the status information to the non-volatile memory. A port is provided on the integrated circuit coupled to the non-volatile memory through which the status information stored in the non-volatile memory is accessible in a test read mode to external devices. In a FLASH EPROM embodiment, the IC includes an array of FLASH EPROM memory cells and a port through which data in the array is accessible by external devices. A test set of FLASH EPROM memory cells is provided in the array. Program and erase circuitry, coupled to the array, has a test mode to exercise the program and erase circuitry to generate status information indicating results of the test and test read mode to read out the status information. Non-volatile status write circuitry, is coupled to the program and erase circuitry and the test set, and writes the status information to the test set. The program and erase circuits include retry counts with programmable thresholds for reducing the test times of the devices.

摘要翻译： 集成电路包括诸如具有自动编程和擦除电路的闪存的功能模块，与功能模块耦合的测试电路，其执行功能模块的测试并且作为测试的结果生成状态信息，以及非易失性状态 写入电路与芯片上的测试电路耦合。 非易失性状态写入电路中的电路响应于功能电路的测试以将状态信息写入非易失性存储器。 在与非易失性存储器耦合的集成电路上提供端口，通过该端口，存储在非易失性存储器中的状态信息可以以测试读取模式访问到外部设备。 在FLASH EPROM实施例中，IC包括闪存EPROM存储器单元阵列和阵列中的数据可由外部设备访问的端口。 阵列中提供了一组FLASH EPROM存储单元。 耦合到阵列的编程和擦除电路具有运行程序和擦除电路的测试模式，以产生指示测试结果的状态信息和测试读取模式以读出状态信息。 非易失性状态写入电路耦合到程序和擦除电路和测试仪，并将状态信息写入测试仪。 程序和擦除电路包括具有可编程阈值的重试计数，以减少器件的测试时间。

公开(公告)号：US5691945A

公开(公告)日：1997-11-25

申请号：US605100

申请日：1996-03-01

申请人： Kong-Mou Liou ,  Tom Dang-Hsing Yiu ,  Ray-Lin Wan ,  Yao-Wu Cheng ,  Chun-Hsiung Hung ,  Ting-Chung Hu ,  Tien-Ler Lin

发明人： Kong-Mou Liou ,  Tom Dang-Hsing Yiu ,  Ray-Lin Wan ,  Yao-Wu Cheng ,  Chun-Hsiung Hung ,  Ting-Chung Hu ,  Tien-Ler Lin

IPC分类号： G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C29/00 ,  G11C7/00

CPC分类号： G11C29/76 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12

摘要： A flexible technique for improving yield of manufacturing of high density of memory devices, such as flash EEPROM, involves reconfiguring an integrated circuit memory array having a plurality of sectors selected by an address decoder in response to an N bit field in an address. If defective sectors are detected in the array, it is partitioned to disable defective sectors by configuring a sector decoder to prevent access to the defective sectors while maintaining sequential addressing remaining sectors in the array. The step of partitioning includes configuring the sector decoder to replace a defective sector in one half of the array by another sector in the other half of the array having N-m of the N address bits in common with the defective sector when m is between 1 and N-1.

摘要翻译： PCT No.PCT / US95 / 06990第 371日期1996年3月1日 102（e）1996年3月1日PCT 1995年5月31日PCT PCT。 公开号WO96 / 38845 日期1996年12月5日用于提高高密度存储器件（例如闪存EEPROM）的制造成品率的灵活技术涉及重新配置具有由地址解码器选择的多个扇区的集成电路存储器阵列，以响应于N位字段 一个地址 如果在阵列中检测到有缺陷的扇区，则通过配置扇区解码器以防止对阵列中的剩余扇区的顺序寻址，同时对阵列解码器进行划分以禁用缺陷扇区。 分割步骤包括配置扇区解码器以在阵列的另一半中的另外一个扇区替换阵列的一半中的缺陷扇区，其中，当m在1和N之间时，具有与缺陷扇区相同的N个地址位的Nm -1。

公开(公告)号：US5778440A

公开(公告)日：1998-07-07

申请号：US596380

申请日：1996-02-16

申请人： Tom Dang-Hsing Yiu ,  Ray-Lin Wan ,  Yao-Wu Cheng ,  Chung-Hsiung Hung ,  Fuchia Shone

发明人： Tom Dang-Hsing Yiu ,  Ray-Lin Wan ,  Yao-Wu Cheng ,  Chung-Hsiung Hung ,  Fuchia Shone

IPC分类号： G11C16/04 ,  G11C16/32 ,  G11C16/34 ,  G06F13/00 ,  G11C16/06

CPC分类号： G11C16/0491 ,  G08G1/017 ,  G11C16/32 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521

摘要： A floating gate memory with a protocol which terminates a program load cycle upon detecting a predetermined address and/or data pattern, providing positive indication of the end of the load cycle, and eliminating the requirement for a long pulse in a controlled signal. Command logic executes a process to store a block of data in response to a sequence of addresses and data segments received at the input/output circuitry, and detects the last segment in a block of data in response to a pattern including at least one of the addresses and data segments received at the input/output circuitry. One pattern includes consecutive matching addresses. Pattern match logic included in the command logic is coupled to the input/output circuitry and stores addresses in the sequence and compares them with a next address to indicate a matching address. Alternatively, the pattern includes both matching addresses and data segments with corresponding comparator circuitry. Alternatively, the pattern comprises a command address which is outside the address field of the memory array. The command address may include all or only a high order segment of the actual data address. The floating gate memory includes a state machine which automatically programs and verifies programming of the block of data after the last segment of the block is detected, and may comprise a flash memory or electrically erasable programmable read only memory (EEPROM).

摘要翻译： PCT No.PCT / US95 / 06762 Sec。 371日期1996年2月16日 102（e）日期1996年2月16日PCT 1995年5月26日提交具有协议的浮动门存储器，其在检测到预定地址和/或数据模式时终止程序加载周期，提供负载循环结束的正向指示， 并消除了对受控信号中的长脉冲的要求。 响应于在输入/输出电路处接收的地址和数据段的序列，命令逻辑执行存储数据块的过程，并响应于包括至少一个的模式来检测数据块中的最后一个段 在输入/输出电路处接收的地址和数据段。 一种模式包括连续的匹配地址。 包括在命令逻辑中的模式匹配逻辑被耦合到输入/输出电路，并且存储序列中的地址，并将它们与下一个地址进行比较以指示匹配的地址。 或者，该模式包括具有对应的比较器电路的匹配地址和数据段。 或者，该模式包括在存储器阵列的地址字段之外的命令地址。 命令地址可以包括实际数据地址的全部或仅有高阶段。 浮动门存储器包括在检测到块的最后段之后自动编程和验证数据块的编程的状态机，并且可以包括闪速存储器或电可擦除可编程只读存储器（EEPROM）。

公开(公告)号：US5745410A

公开(公告)日：1998-04-28

申请号：US619485

申请日：1996-03-21

申请人： Tom Dang-Hsing Yiu ,  Fuchia Shone ,  I-Long Lee ,  Chia-Shing Chen ,  Hun-Song Chen ,  Yuan-Chang Liu ,  Tzeng-Huei Shiau ,  Kuen-Long Chang ,  Ray-Lin Wan

发明人： Tom Dang-Hsing Yiu ,  Fuchia Shone ,  I-Long Lee ,  Chia-Shing Chen ,  Hun-Song Chen ,  Yuan-Chang Liu ,  Tzeng-Huei Shiau ,  Kuen-Long Chang ,  Ray-Lin Wan

IPC分类号： G11C11/40

CPC分类号： G11C11/40

摘要： A floating gate memory device which includes control circuits to generate a repair pulse to repair over-erased cells so they may be repaired block-by-block. This invention includes repairing the cells by applying a repair pulse to the cell's bit line while maintaining the word line voltage above ground. In a different embodiment, the word line voltage is maintained at two different voltage levels above ground. In the first stage, the word line voltage is maintained between approximately 0.1 volts and 0.2 volts for approximately 100 ms while the repair pulse is applied. In the second stage, the word line voltage is maintained between approximately 0.4 volts and 0.5 volts for approximately 100 ms while the repair pulse is applied.

摘要翻译： PCT No.PCT / US95 / 15051 Sec。 371日期1996年3月21日 102（e）1996年3月21日PCT 1995年11月17日PCT PCT。 第WO97 / 19452号公报 日期1997年5月29日一种浮动栅极存储器件，其包括产生修复脉冲以修复过擦除的单元的控制电路，使得它们可以逐块修复。 本发明包括通过在维持字线电压高于地面的同时将修复脉冲施加到单元的位线来修复单元。 在不同的实施例中，字线电压保持在地面以上两个不同的电压电平。 在第一阶段，当施加修复脉冲时，字线电压保持在大约0.1伏和0.2伏之间大约100毫秒。 在第二阶段，当施加修复脉冲时，字线电压保持在大约0.4伏和0.5伏之间大约100毫秒。

公开(公告)号：US5949704A

公开(公告)日：1999-09-07

申请号：US983526

申请日：1997-04-02

申请人： Fu-Chia Shone ,  Tom Dang-Hsing Yiu

发明人： Fu-Chia Shone ,  Tom Dang-Hsing Yiu

IPC分类号： H01L21/8246 ,  H01L27/112 ,  G11C17/00

CPC分类号： H01L27/112

摘要： A stacked ROM device utilizes the same conductivity type for the ROM cells in both the top and the bottom ROM cell matrixes. The stacked ROM device comprises a first ROM cell matrix which comprises conductively doped source and drain lines having a first conductivity type in a semiconductor substrate having a second conductivity type. For example, the source and drain lines are implemented with n-type doping in a p-type substrate. A second ROM cell matrix comprises conductively doped source and drain lines having the first conductivity type in a semiconductor layer which overlies and is isolated from the semiconductor substrate. A plurality of shared wordlines is disposed between the first and second ROM cell matrixes. A plurality of bit lines is isolated from and overlies the semiconductor layer. A plurality of matrix select transistors is coupled between the conductively doped source and drain lines in the first ROM cell matrix and the plurality of bit lines, and between the conductively doped source and drain lines in the second ROM cell matrix and the plurality of bit lines, to selectively connect the first ROM cell matrix and the second ROM cell matrix to the plurality of bit lines.

摘要翻译： PCT No.PCT / US96 / 14685第 371日期1997年4月2日 102（e）1997年4月2日PCT PCT 1996年9月10日PCT公布。 公开号WO98 / 11607 日期1998年3月19日堆叠的ROM器件对于顶部和底部ROM单元矩阵中的ROM单元使用相同的导电类型。 堆叠的ROM器件包括第一ROM单元矩阵，其包括在具有第二导电类型的半导体衬底中具有第一导电类型的导电掺杂源极和漏极线。 例如，源极和漏极线在p型衬底中用n型掺杂实现。 第二ROM单元矩阵包括在半导体层中具有第一导电类型的导电掺杂源极和漏极线，该半导体层覆盖并与半导体衬底隔离。 多个共享字线被布置在第一和第二ROM单元矩阵之间。 多个位线与半导体层隔离并覆盖半导体层。 多个矩阵选择晶体管耦合在第一ROM单元矩阵和多个位线中的导电掺杂源极线和漏极线之间以及第二ROM单元矩阵中的导电掺杂源极和漏极线之间以及多个位线 选择性地将第一ROM单元矩阵和第二ROM单元矩阵连接到多个位线。

公开(公告)号：US5668758A

公开(公告)日：1997-09-16

申请号：US612923

申请日：1996-03-05

申请人： Tom Dang-Hsing Yiu ,  Chun-Hsiung Hung ,  Ray-Lin Wan ,  Yao-Wu Cheng ,  Teruhiko Kamei

发明人： Tom Dang-Hsing Yiu ,  Chun-Hsiung Hung ,  Ray-Lin Wan ,  Yao-Wu Cheng ,  Teruhiko Kamei

IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C8/08 ,  G11C16/02 ,  G11C16/06 ,  G11C16/08 ,  G11C16/12 ,  G11C7/00

CPC分类号： G11C16/08 ,  G11C16/12 ,  G11C5/143 ,  G11C8/08

摘要： Wordline driver circuitry drives a plurality of wordlines in a flash EEPROM memory array in a first mode which selects between a positive voltage and ground, and a second mode which selects between a negative voltage and ground. A first supply voltage selector supplies positive voltage during the first mode, and a second mode reference voltage, such as ground, in the second mode. A second supply voltage selector supplies the first mode reference voltage such as ground in the first mode, and the negative voltage during a second mode. An inverting driver has an input which receives a wordline select signal, and an output coupled to the wordline, a first supply voltage input connected to the first supply voltage selector, and second supply voltage input connected to the second supply voltage selector. The inverting driver couples the first supply voltage input to the wordline when the wordline select signal is in a low state, and couples the second supply voltage input to the wordline when the wordline select signal is in a high state. A second inverter is connected in feedback across the inverting driver to hold the input of the inverting driver at the value of the wordline select signal during the negative voltage decode. The wordline select signals come from an address decoder. An isolation circuit is provided between the address decoder and the input to the inverting driver to isolate the decoder from the negative voltages which appear on the output of the second inverter during the negative voltage decoding state.

摘要翻译： PCT No.PCT / US95 / 01031 Sec。 371日期：1996年3月5日 102（e）1996年3月5日PCT 1995年1月26日PCT PCT。 公开号WO96 / 23307 日期1996年8月1日沃尔金斯司机电路以第一模式驱动闪存EEPROM存储器阵列中的多个字线，该第一模式在正电压和地之间进行选择，第二模式在负电压和地之间进行选择。 第一电源电压选择器在第一模式下提供正电压，在第二模式中提供第二模式参考电压，例如接地。 第二电源电压选择器在第一模式下提供诸如接地的第一模式参考电压，在第二模式期间提供负电压。 反相驱动器具有接收字线选择信号的输入和耦合到字线的输出，连接到第一电源电压选择器的第一电源电压输入和连接到第二电源电压选择器的第二电源电压输入。 当字线选择信号处于低状态时，反相驱动器将第一电源电压输入耦合到字线，并且当字线选择信号处于高状态时，将第二电源电压输入耦合到字线。 第二反相器通过反相驱动器反馈连接，以在负电压解码期间将反相驱动器的输入保持在字线选择信号的值。 字线选择信号来自地址解码器。 在地址解码器和反相驱动器的输入端之间设置隔离电路，以将解码器与在负电压解码状态期间出现在第二反相器的输出端上的负电压隔离。