公开(公告)号：US06756262B1

公开(公告)日：2004-06-29

申请号：US09708450

申请日：2000-11-09

申请人： Yoshitaka Nakamura ,  Isamu Asano ,  Satoru Yamada ,  Tsugio Takahashi ,  Yuzuru Ohji ,  Masayoshi Hirasawa ,  Takashi Yunogami ,  Tomonori Sekiguchi

发明人： Yoshitaka Nakamura ,  Isamu Asano ,  Satoru Yamada ,  Tsugio Takahashi ,  Yuzuru Ohji ,  Masayoshi Hirasawa ,  Takashi Yunogami ,  Tomonori Sekiguchi

IPC分类号： H01L218249

CPC分类号： H01L28/75 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10894 ,  H01L28/55 ,  H01L28/65 ,  H01L28/90

摘要： Conduction reliability between a capacitor upper electrode and a plug connected to an upper layer wire is kept high to prevent connection defects and to reduce the resistance of the capacitor upper electrode. In a capacitor of a DRAM comprising a lower electrode 45 made of ruthenium, a capacitor insulating film 50 made of BST and an upper electrode 49, the upper electrode 49 has a laminate structure comprising a ruthenium film 47 formed on the side of the capacitor insulating film 50 and a tungsten film 48 formed over the former.

摘要翻译： 电容器上部电极和连接到上层电线的插头之间的传导可靠性保持较高，以防止连接缺陷并降低电容器上部电极的电阻。 在包括由钌制成的下电极45的电容器，由BST制成的电容器绝缘膜50和上电极49的情况​​下，上电极49具有包括形成在绝缘电容器侧的钌膜47的层叠结构 膜50和形成在前者上的钨膜48。

公开(公告)号：US06426255B1

公开(公告)日：2002-07-30

申请号：US09549085

申请日：2000-04-13

申请人： Isamu Asano ,  Yoshitaka Nakamura ,  Yuzuru Ohji ,  Tatsuyuki Saito ,  Takashi Yunogami

发明人： Isamu Asano ,  Yoshitaka Nakamura ,  Yuzuru Ohji ,  Tatsuyuki Saito ,  Takashi Yunogami

IPC分类号： H01L218242

CPC分类号： H01L27/10894 ,  H01L21/2885 ,  H01L27/10814 ,  H01L27/10882 ,  H01L28/55 ,  H01L28/60

摘要： After formation of a groove in a silicon oxide film, a Pt film is formed inside of the groove by electroplating using a conductive underlying film, which has been formed in advance below the silicon oxide film, as a cathode electrode. The silicon oxide film is then removed by etching, followed by dry etching of the conductive underlying film with the Pt film as a mask, whereby a lower electrode of a capacitor is formed from the Pt film and the conductive underlying film which has remained below the Pt film.

摘要翻译： 在氧化硅膜中形成沟槽之后，通过使用在氧化硅膜之前预先形成的导电性底膜进行电镀而在沟槽内部形成Pt膜作为阴极电极。 然后通过蚀刻去除氧化硅膜，然后用Pt膜作为掩模对导电性底膜进行干蚀刻，由此由Pt膜和导电性底层膜形成电容器的下电极，该电极保持在低于 Pt膜。

公开(公告)号：US06326218B1

公开(公告)日：2001-12-04

申请号：US09575442

申请日：2000-05-22

申请人： Takashi Yunogami ,  Kazuo Nojiri ,  Yuzuru Ohji ,  Sukeyoshi Tsunekawa ,  Masahiko Hiratani ,  Yuichi Matsui

发明人： Takashi Yunogami ,  Kazuo Nojiri ,  Yuzuru Ohji ,  Sukeyoshi Tsunekawa ,  Masahiko Hiratani ,  Yuichi Matsui

IPC分类号： H01G706

CPC分类号： H01L27/105 ,  H01L21/32139 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/11509 ,  H01L28/55 ,  H01L28/60

摘要： Described is a manufacturing method of an integrated circuit which uses a thin film such as platinum or BST as a hard mask upon patterning ruthenium or the like, thereby making it possible to form a device without removing the hard mask. In addition, the invention method makes it possible to interpose a protecting film such as platinum in order to prevent, upon removing a resist used for the patterning of the hard mask, an underlying ruthenium film or the like from being damaged.

摘要翻译： 描述了在图案化钌等上使用诸如铂或BST之类的薄膜作为硬掩模的集成电路的制造方法，从而可以在不去除硬掩模的情况下形成器件。 另外，本发明的方法可以插入诸如铂的保护膜，以便在去除用于图案化硬掩模的抗蚀剂时，下面的钌膜等被损坏。

公开(公告)号：US06451665B1

公开(公告)日：2002-09-17

申请号：US09459343

申请日：1999-12-13

申请人： Takashi Yunogami ,  Kazuo Nojiri ,  Yuzuru Ohji ,  Sukeyoshi Tsunekawa ,  Masahiko Hiratani ,  Yuichi Matsui

发明人： Takashi Yunogami ,  Kazuo Nojiri ,  Yuzuru Ohji ,  Sukeyoshi Tsunekawa ,  Masahiko Hiratani ,  Yuichi Matsui

IPC分类号： H01L2120

CPC分类号： H01L27/105 ,  H01L21/32139 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/11509 ,  H01L28/55 ,  H01L28/60

摘要： Described is a manufacturing method of an integrated circuit which uses a thin film such as platinum or BST as a hard mask upon patterning ruthenium or the like, thereby making it possible to form a device without removing the hard mask. In addition, the invention method makes it possible to interpose a protecting film such as platinum in order to prevent, upon removing a resist used for the patterning of the hard mask, an underlying ruthenium film or the like from being damaged.

摘要翻译： 描述了在图案化钌等上使用诸如铂或BST之类的薄膜作为硬掩模的集成电路的制造方法，从而可以在不去除硬掩模的情况下形成器件。 另外，本发明的方法可以插入诸如铂的保护膜，以便在去除用于图案化硬掩模的抗蚀剂时，下面的钌膜等被损坏。

公开(公告)号：US06607988B2

公开(公告)日：2003-08-19

申请号：US09749554

申请日：2000-12-28

申请人： Takashi Yunogami ,  Yoshitaka Nakamura ,  Kazuo Nojiri ,  Sukeyoshi Tsunekawa ,  Toshiyuki Arai ,  Miwako Nakahara ,  Shigeru Ohno ,  Tomonori Saeki ,  Masaru Izawa

发明人： Takashi Yunogami ,  Yoshitaka Nakamura ,  Kazuo Nojiri ,  Sukeyoshi Tsunekawa ,  Toshiyuki Arai ,  Miwako Nakahara ,  Shigeru Ohno ,  Tomonori Saeki ,  Masaru Izawa

IPC分类号： H01L21302

CPC分类号： H01L28/65 ,  C23F4/00 ,  H01L21/32136 ,  H01L27/10814 ,  H01L27/10852 ,  H01L28/91

摘要： With a view to providing a technique for highly-selective etching of Ru (ruthenium) using a photoresist as an etching mask, an Ru-film, which is an lower electrode material deposited on the side walls and bottom surface of a hole, is covered with a photoresist film, followed by isotropic dry etching in a gas atmosphere containing an ozone gas, whereby a portion of the Ru film outside of the hole is removed.

摘要翻译： 为了提供使用光致抗蚀剂作为蚀刻掩模对Ru（钌）进行高选择性蚀刻的技术，覆盖沉积在孔的侧壁和底表面上的下电极材料的Ru膜被覆盖 与光致抗蚀剂膜接触，然后在含有臭氧气体的气体气氛中进行各向同性的干法蚀刻，由此除去孔外部的Ru膜的一部分。

公开(公告)号：US20050186801A1

公开(公告)日：2005-08-25

申请号：US11104441

申请日：2005-04-13

申请人： Shouochi Uno ,  Atsushi Maekawa ,  Takashi Yunogami ,  Kazutami Tago ,  Kazuo Nojiri ,  Shuntaro Machida ,  Takafumi Tokunaga

发明人： Shouochi Uno ,  Atsushi Maekawa ,  Takashi Yunogami ,  Kazutami Tago ,  Kazuo Nojiri ,  Shuntaro Machida ,  Takafumi Tokunaga

IPC分类号： H01L21/3065 ,  H01L21/311 ,  H01L21/312 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/02126 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/3122 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76829 ,  H01L21/76835

摘要： In a process for the manufacture of a semiconductor integrated circuit device having an inlaid interconnect structure by embedding a conductor film in a recess, such as a trench or hole, formed in an organic insulating film which constitutes an interlevel dielectric film and includes an organosiloxane as a main component, the recess, such as a trench or hole, is formed by subjecting the organic insulating film to plasma dry etching in a CF-based gas/N2/Ar gas in order to suppress the formation of an abnormal shape on the bottom of the recess, upon formation of a photoresist film over the organic insulating film, followed by formation of the recess therein with the photoresist film as an etching mask.

摘要翻译： 在制造具有嵌入式互连结构的半导体集成电路器件的方法中，通过将导体膜嵌入形成在构成层间电介质膜的有机绝缘膜中的凹槽（例如沟槽或孔）中，并且包括有机硅氧烷作为 通过使有机绝缘膜在基于CF的气体/ N 2 / Ar气中进行等离子体干蚀刻来形成主要部件，凹槽，例如沟槽或孔，以便抑制 在凹陷的底部形成异常形状，在有机绝缘膜上形成光致抗蚀剂膜，然后用光致抗蚀剂膜作为蚀刻掩模形成凹部。

公开(公告)号：US06497992B1

公开(公告)日：2002-12-24

申请号：US09551615

申请日：2000-04-17

申请人： Takashi Yunogami ,  Shunji Sasabe ,  Kazuyuki Suko ,  Jun Abe ,  Takao Kumihashi ,  Fumio Murai

发明人： Takashi Yunogami ,  Shunji Sasabe ,  Kazuyuki Suko ,  Jun Abe ,  Takao Kumihashi ,  Fumio Murai

IPC分类号： G03F726

CPC分类号： H01L21/02071 ,  G03F7/40 ,  H01L21/0274 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/32139

摘要： In order that reaction products of low vapor pressure may be prevented from being deposited on the side wall of a predetermined pattern when this pattern is to be formed by dry-etching a Pt film or a PZT film, a resist mask 54 having a rounded outer periphery at its head is used when the Pt film 53 deposited on a semiconductor substrate 50 is to be dry-etched. After this dry-etching, moreover, an overetching of a proper extent is performed to completely remove the side wall deposited film 55 which is left on the side of the pattern. The resist mask 54 is formed by exposing and developing a benzophenone novolak resist and subsequently by heating to set it while irradiating it, if necessary, with ultraviolet rays.

摘要翻译： 为了防止当通过干法蚀刻Pt膜或PZT膜而形成该图案时，可以防止低蒸气压的反应产物沉积在预定图案的侧壁上，具有圆形外部的抗蚀剂掩模54 当要沉积在半导体衬底50上的Pt膜53被干蚀刻时，使用其头部周边。 此外，在该干蚀刻之后，进行适当程度的过蚀刻以完全去除留在图案侧的侧壁沉积膜55。 抗蚀剂掩模54通过曝光和显影二苯甲酚酚醛清漆抗蚀剂而形成，随后通过加热固化，同时照射它，如果需要，用紫外线照射。

公开(公告)号：US5284544A

公开(公告)日：1994-02-08

申请号：US599018

申请日：1990-10-17

申请人： Tatsumi Mizutani ,  Takashi Yunogami

发明人： Tatsumi Mizutani ,  Takashi Yunogami

IPC分类号： H01L21/302 ,  H01J37/32 ,  H01L21/205 ,  H01L21/3065 ,  H01L21/00

CPC分类号： H01J37/32357

摘要： An apparatus for surface treatment according to the present invention used for carrying out dry etching, thin film deposition and so forth is provided with a neutral beam etching apparatus in order to improve etching rate. In an embodiment, microwave wave-guides forming a duplex tube, a discharge tube, a pair of solenoids arranged coaxially, a multiaperture electrode for extracting an ion beam, gas supply pipes, a set of charged particle retarding grids, a device for controlling temperature of a specimen and a vacuum unit are provided.

摘要翻译： 用于进行干蚀刻，薄膜沉积等的根据本发明的用于表面处理的设备设置有中性束蚀刻装置，以提高蚀刻速率。 在一个实施例中，形成双相管，放电管，同轴布置的一对螺线管的微波波导，用于提取离子束的多孔电极，气体供给管，一组带电粒子延迟栅，用于控制温度的装置 的试样和真空装置。

公开(公告)号：US5314839A

公开(公告)日：1994-05-24

申请号：US756274

申请日：1991-09-06

申请人： Tatsumi Mizutani ,  Takashi Yunogami ,  Kenetsu Yokokawa ,  Nobuyoshi Kobayashi

发明人： Tatsumi Mizutani ,  Takashi Yunogami ,  Kenetsu Yokokawa ,  Nobuyoshi Kobayashi

IPC分类号： H01L21/00 ,  H01L21/3105 ,  H01L21/314 ,  H01L21/316 ,  H01L21/26

CPC分类号： H01L21/67132 ,  H01L21/3105 ,  H01L21/314 ,  Y10S148/076

摘要： To improve the characteristics of oxides and other insulators formed by conventional techniques, particularly to improve its density, relative dielectric constant, resistance to acid, resistance to reduction and other characteristics, and to provide solid state devices or socharacteristics, the surfaces of the silicon oxide insulator, or the like, is irradiated with electrically neutral particles.

摘要翻译： 为了改善通过常规技术形成的氧化物和其它绝缘体的特性，特别是提高其密度，相对介电常数，耐酸性，耐还原性等特性，以及提供固态器件或特性，氧化硅表面 绝缘体等被电中性粒子照射。

公开(公告)号：US5241186A

公开(公告)日：1993-08-31

申请号：US552119

申请日：1990-07-13

申请人： Takashi Yunogami ,  Tatsumi Mizutani ,  Keizo Suzuki

发明人： Takashi Yunogami ,  Tatsumi Mizutani ,  Keizo Suzuki

IPC分类号： H01L21/31 ,  G01Q30/08 ,  H01L21/30 ,  H01L21/3105 ,  H01L21/316

CPC分类号： H01L21/3105

摘要： A method of preventing damages of a semiconductor having an insulator film at its surface caused by holes induced in the insulator film and move to and are trapped at or near the interface between the insulator film and a substrate upon applying surface treatment for the surface of the semiconductor, as well as an apparatus suitable to practicing the method are disclosed. The surface treatment method comprises trapping to eliminate the holes in the insulator film by an electric field before the movement of the holes at or near the interface, neutralizing the induced holes by re-combination, or previously forming a hole trapping level in the insulator film thereby trapping the induced holes to the trapping level, etc.