公开(公告)号：US07652935B2

公开(公告)日：2010-01-26

申请号：US12076787

申请日：2008-03-24

申请人： Tomoya Ogawa ,  Takashi Ito ,  Hidenori Mitani ,  Takashi Kono

发明人： Tomoya Ogawa ,  Takashi Ito ,  Hidenori Mitani ,  Takashi Kono

IPC分类号： G11C7/22

CPC分类号： G11C16/3404

摘要： When a data write sequence is started, initially, write data is latched in a data latch circuit corresponding to one memory mat. Then, a program pulse is applied to the memory mat, and data read from a memory cell, which is a data write target bit in the memory mat, is performed. Thereafter, verify determination of the memory mat is performed. After a verify operation for the memory mat is completed, a program pulse is applied to another memory mat, and a verify operation for another memory mat is performed.

摘要翻译： 当数据写入序列开始时，最初写入数据被锁存在对应于一个存储器垫的数据锁存电路中。 然后，将程序脉冲施加到存储器垫，并且执行从作为存储器垫中的数据写入目标位的存储单元读取的数据。 此后，验证是否执行存储垫的确定。 在存储器垫的验证操作完成之后，将程序脉冲施加到另一个存储器垫，并且执行另一存储器垫的验证操作。

公开(公告)号：US20080239826A1

公开(公告)日：2008-10-02

申请号：US12076787

申请日：2008-03-24

申请人： Tomoya Ogawa ,  Takashi Ito ,  Hidenori Mitani ,  Takashi Kono

发明人： Tomoya Ogawa ,  Takashi Ito ,  Hidenori Mitani ,  Takashi Kono

IPC分类号： G11C16/34

CPC分类号： G11C16/3404

摘要： When a data write sequence is started, initially, write data is latched in a data latch circuit corresponding to one memory mat. Then, a program pulse is applied to the memory mat, and data read from a memory cell, which is a data write target bit in the memory mat, is performed. Thereafter, verify determination of the memory mat is performed. After a verify operation for the memory mat is completed, a program pulse is applied to another memory mat, and a verify operation for another memory mat is performed.

摘要翻译： 当数据写入序列开始时，最初写入数据被锁存在对应于一个存储器垫的数据锁存电路中。 然后，将程序脉冲施加到存储器垫，并且执行从作为存储器垫中的数据写入目标位的存储单元读取的数据。 此后，验证是否执行存储垫的确定。 在存储器垫的验证操作完成之后，将程序脉冲施加到另一个存储器垫，并且执行另一存储器垫的验证操作。

公开(公告)号：US20070242519A1

公开(公告)日：2007-10-18

申请号：US11812704

申请日：2007-06-21

申请人： Takashi Ito ,  Hidenori Mitani

发明人： Takashi Ito ,  Hidenori Mitani

IPC分类号： G11C16/34

CPC分类号： G11C16/14 ,  G11C16/3404 ,  G11C16/344

摘要： According to a method of erasing data in a non-volatile semiconductor memory device, block-round type overerase verify is performed. Specifically, overerase verify and write back are performed sequentially from a first address to a last address. That is, even when a write back pulse is applied after a certain address is selected and verify is performed, address increment from one address to another is performed, regardless of whether verify has been performed or not. Therefore, it is not that the same address is cumulatively rewritten, but write back to a memory cell corresponding to a defective address is sequentially and gradually performed. Accordingly, as write to a memory cell in an overerased state can evenly be performed, influence by off-leakage is suppressed, and a memory cell having threshold voltage distribution with less variation can be implemented.

摘要翻译： 根据擦除非易失性半导体存储器件中的数据的方法，执行块式过程验证。 具体来说，过度验证和回写是从第一个地址到最后一个地址顺序执行的。 也就是说，即使在选择了某个地址并进行验证之后应用写回脉冲的情况下，执行从一个地址到另一个地址的地址增量，而不管是否执行了验证。 因此，不是相同的地址被累积地重写，而是顺序地逐渐执行写入与缺陷地址对应的存储单元。 因此，能够均匀地进行对高电平状态的存储单元的写入，能够抑制泄漏的影响，能够实现具有小变化的阈值电压分布的存储单元。

公开(公告)号：US07499337B2

公开(公告)日：2009-03-03

申请号：US11812704

申请日：2007-06-21

申请人： Takashi Ito ,  Hidenori Mitani

发明人： Takashi Ito ,  Hidenori Mitani

IPC分类号： G11C16/00

CPC分类号： G11C16/14 ,  G11C16/3404 ,  G11C16/344

摘要： According to a method of erasing data in a non-volatile semiconductor memory device, block-round type overerase verify is performed. Specifically, overerase verify and write back are performed sequentially from a first address to a last address. That is, even when a write back pulse is applied after a certain address is selected and verify is performed, address increment from one address to another is performed, regardless of whether verify has been performed or not. Therefore, it is not that the same address is cumulatively rewritten, but write back to a memory cell corresponding to a defective address is sequentially and gradually performed. Accordingly, as write to a memory cell in an overerased state can evenly be performed, influence by off-leakage is suppressed, and a memory cell having threshold voltage distribution with less variation can be implemented.

摘要翻译： 根据擦除非易失性半导体存储器件中的数据的方法，执行块式过程验证。 具体来说，过度验证和回写是从第一个地址到最后一个地址顺序执行的。 也就是说，即使在选择了某个地址并进行验证之后应用写回脉冲的情况下，执行从一个地址到另一个地址的地址增量，而不管是否执行了验证。 因此，不是相同的地址被累积地重写，而是顺序地逐渐执行写入与缺陷地址对应的存储单元。 因此，能够均匀地进行对高电平状态的存储单元的写入，能够抑制泄漏的影响，能够实现具有小变化的阈值电压分布的存储单元。

公开(公告)号：US20060158939A1

公开(公告)日：2006-07-20

申请号：US11328224

申请日：2006-01-10

申请人： Takashi Ito ,  Hidenori Mitani

发明人： Takashi Ito ,  Hidenori Mitani

IPC分类号： G11C16/04

CPC分类号： G11C16/14 ,  G11C16/3404 ,  G11C16/344

摘要： According to a method of erasing data in a non-volatile semiconductor memory device, block-round type overerase verify is performed. Specifically, overerase verify and write back are performed sequentially from a first address to a last address. That is, even when a write back pulse is applied after a certain address is selected and verify is performed, address increment from one address to another is performed, regardless of whether verify has been performed or not. Therefore, it is not that the same address is cumulatively rewritten, but write back to a memory cell corresponding to a defective address is sequentially and gradually performed. Accordingly, as write to a memory cell in an overerased state can evenly be performed, influence by off-leakage is suppressed, and a memory cell having threshold voltage distribution with less variation can be implemented.

公开(公告)号：US07236406B2

公开(公告)日：2007-06-26

申请号：US11328224

申请日：2006-01-10

申请人： Takashi Ito ,  Hidenori Mitani

发明人： Takashi Ito ,  Hidenori Mitani

IPC分类号： G11C16/34

CPC分类号： G11C16/14 ,  G11C16/3404 ,  G11C16/344

摘要： According to a method of erasing data in a non-volatile semiconductor memory device, block-round type overerase verify is performed. Specifically, overerase verify and write back are performed sequentially from a first address to a last address. That is, even when a write back pulse is applied after a certain address is selected and verify is performed, address increment from one address to another is performed, regardless of whether verify has been performed or not. Therefore, it is not that the same address is cumulatively rewritten, but write back to a memory cell corresponding to a defective address is sequentially and gradually performed. Accordingly, as write to a memory cell in an overerased state can evenly be performed, influence by off-leakage is suppressed, and a memory cell having threshold voltage distribution with less variation can be implemented.

公开(公告)号：US20150131384A1

公开(公告)日：2015-05-14

申请号：US14400500

申请日：2012-08-29

申请人： Tomoya Ogawa ,  Takashi Ito ,  Mitsuhiro Tomoeda

发明人： Tomoya Ogawa ,  Takashi Ito ,  Mitsuhiro Tomoeda

IPC分类号： G11C16/14

CPC分类号： G11C16/14 ,  G11C16/06 ,  G11C16/12 ,  G11C16/30 ,  G11C16/32

摘要： In a nonvolatile memory device (4) provided in a semiconductor device, when data is erased based on a band-to-band tunneling scheme, supply of a boosted voltage to a memory cell (MC) to be erased is ended when a condition that an output voltage (VUCP) of a charge pump circuit (52) has recovered to a predetermined reference voltage is satisfied and additionally a condition that a predetermined reference time has elapsed since start of supply of the boosted voltage (VUCP) to the memory cell (MC) to be erased is satisfied.

摘要翻译： 在设置在半导体器件中的非易失性存储器件（4）中，当基于带 - 带隧穿方案擦除数据时，在被擦除的存储器单元（MC）中提供升压电压将在 已经恢复到预定参考电压的电荷泵电路（52）的输出电压（VUCP）被满足，并且另外还有一个从提升升压电压（VUCP）开始到存储单元（VUCP）开始经过了预定基准时间的条件 MC）被清除。

公开(公告)号：US09177657B2

公开(公告)日：2015-11-03

申请号：US14400500

申请日：2012-08-29

申请人： Tomoya Ogawa ,  Takashi Ito ,  Mitsuhiro Tomoeda

发明人： Tomoya Ogawa ,  Takashi Ito ,  Mitsuhiro Tomoeda

IPC分类号： G11C16/04 ,  G11C16/14 ,  G11C16/06 ,  G11C16/32

CPC分类号： G11C16/14 ,  G11C16/06 ,  G11C16/12 ,  G11C16/30 ,  G11C16/32

摘要： In a nonvolatile memory device (4) provided in a semiconductor device, when data is erased based on a band-to-band tunneling scheme, supply of a boosted voltage to a memory cell (MC) to be erased is ended when a condition that an output voltage (VUCP) of a charge pump circuit (52) has recovered to a predetermined reference voltage is satisfied and additionally a condition that a predetermined reference time has elapsed since start of supply of the boosted voltage (VUCP) to the memory cell (MC) to be erased is satisfied.

摘要翻译： 在设置在半导体器件中的非易失性存储器件（4）中，当基于带 - 带隧穿方案擦除数据时，在被擦除的存储器单元（MC）中提供升压电压将在 已经恢复到预定参考电压的电荷泵电路（52）的输出电压（VUCP）被满足，并且另外还有一个从提升升压电压（VUCP）开始到存储单元（VUCP）开始经过了预定基准时间的条件 MC）被清除。

公开(公告)号：US10230112B2

公开(公告)日：2019-03-12

申请号：US14119308

申请日：2012-05-22

申请人： Yusuke Kato ,  Takashi Ito ,  Masami Yanagida ,  Satoshi Oku ,  Hiroyuki Ogino ,  Masato Kusakabe ,  Ryutaro Mukai ,  Masahiro Kojima ,  Takashi Kikuchi ,  Akiko Waki ,  Shiho Inoue ,  Shigeo Ibuka ,  Yasuyuki Tanaka ,  Yoshio Shimoida ,  Yuji Muroya ,  Norihisa Waki

发明人： Yusuke Kato ,  Takashi Ito ,  Masami Yanagida ,  Satoshi Oku ,  Hiroyuki Ogino ,  Masato Kusakabe ,  Ryutaro Mukai ,  Masahiro Kojima ,  Takashi Kikuchi ,  Akiko Waki ,  Shiho Inoue ,  Shigeo Ibuka ,  Yasuyuki Tanaka ,  Yoshio Shimoida ,  Yuji Muroya ,  Norihisa Waki

IPC分类号： H01M4/66 ,  H01M10/052 ,  H01M4/02

摘要： A conductive film includes a layer 1 formed by a conductive material 1 that includes a polymer material 1 containing any of (1) an amine and an epoxy resin (where the epoxy resin and the amine are mixed in a ratio of 1.0 or more in terms of the ratio of the number of active hydrogen atoms in the amine with respect to the number of functional groups in the epoxy resin), (2) a phenoxy resin and an epoxy resin, (3) a saturated hydrocarbon polymer having a hydroxyl group, and (4) a curable resin and an elastomer and conductive particles 1. The conductive film has excellent stability in an equilibrium potential environment in a negative electrode and low electric resistance per unit area in the thickness direction. A multilayer conductive film including the conductive film achieves excellent interlayer adhesion, and using them as a current collector enables the production of a battery satisfying both weight reduction and durability.

公开(公告)号：US09441676B2

公开(公告)日：2016-09-13

申请号：US14130010

申请日：2012-06-21

申请人： Takashi Ito ,  Naota Yamamoto ,  Tsukasa Yamakawa ,  Hirohide Komatsu ,  Tsutomu Sawa

发明人： Takashi Ito ,  Naota Yamamoto ,  Tsukasa Yamakawa ,  Hirohide Komatsu ,  Tsutomu Sawa

IPC分类号： G08B13/14 ,  F16C41/00 ,  G06K19/07 ,  G06K19/077 ,  H04B5/00 ,  F16C33/58 ,  F16C19/36 ,  F16C43/04

CPC分类号： F16C41/008 ,  F16C19/364 ,  F16C19/548 ,  F16C33/586 ,  F16C43/04 ,  F16C2233/00 ,  F16C2300/02 ,  G06K19/0723 ,  G06K19/07771 ,  H04B5/0056

摘要： A bearing assembly includes an IC tag with information to be reliably exchanged between the IC tag and an external reader/writer, and a rolling bearing including outer and inner races and rolling elements disposed between the outer and inner races. The IC tag communicates with the external reader/writer device without contacting the reader/writer device, is attached to a metal member of the rolling bearing, includes a tag antenna, and is configured so information can be exchanged between the tag antenna and a reader/writer antenna of the reader/writer device by forming a closed magnetic circuit between the tag antenna and the reader/writer antenna. The IC tag is received in a hole in a metal member surface. The tag antenna includes at least two protrusions facing the opening of the hole and arranged so magnetic fluxes leaving/entering the protrusions pass inside the edge defining the hole opening and extend outside the hole.

摘要翻译： 轴承组件包括具有在IC标签和外部读写器之间可靠交换的信息的IC标签，以及包括设置在外圈和内圈之间的外圈和内圈和滚动元件的滚动轴承。 IC标签与外部读/写器设备通信，而不需要接触读/写器设备，连接到滚动轴承的金属构件，包括标签天线，并且被配置为可以在标签天线和读取器之间交换信息 /写入器天线，通过在标签天线和读/写天线之间形成闭合磁路。 IC标签被容纳在金属构件表面的孔中。 标签天线包括面向孔的开口的至少两个突起，并且布置成使得离开/进入突起的磁通在限定孔开口的边缘内部通过并延伸到孔的外部。