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公开(公告)号：USRE47815E1
公开(公告)日：2020-01-14
申请号：US15961148
申请日：2018-04-24
摘要： A nonvolatile semiconductor memory device includes: a memory unit; and a control unit. The memory unit includes: first and second memory strings including first and second memory transistors with first and second select gates, respectively; and first and second wirings connected thereto. In a selective erase operation of a selected cell transistor of the first memory transistors, the control unit applies V1 voltage to the first wiring, applies V2 voltage lower than V1 to a selected cell gate of the selected cell transistor, applies V3 voltage not higher than V1 and higher than V2 to a non-selected cell gate of the first memory transistors, applies V1 or V4 voltage not higher than V1 and not lower than V3 to the first select gate, and applies V2 or V4 voltage higher than V2 and not higher than V3 to the second wiring or sets the second wiring in a floating state.
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公开(公告)号：US10438970B2
公开(公告)日：2019-10-08
申请号：US15980966
申请日：2018-05-16
发明人： Takeshi Sonehara , Masaru Kito
IPC分类号： H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L27/11575
摘要： According to an embodiment, a semiconductor memory device comprises control gate electrodes and a semiconductor layer. The control gate electrodes are stacked above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate. The semiconductor memory device further comprises first and second control gate electrodes and third and fourth control gate electrodes stacked sequentially above the substrate and first through fourth via contacts connected to these first through fourth control gate electrodes. The third and fourth control gate electrodes face the first and second control gate electrodes. Positions of the first and second via contacts are far from each other. Positions of the third and fourth via contacts are close to each other.
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公开(公告)号：US10141327B2
公开(公告)日：2018-11-27
申请号：US15264994
申请日：2016-09-14
发明人： Takeshi Sonehara , Masaru Kito
IPC分类号： H01L27/115 , H01L27/11582 , H01L23/532 , H01L23/528 , H01L27/11573 , H01L49/02 , H01L27/11556
摘要： According to an embodiment, a semiconductor memory device comprises: an insulating layer disposed on a semiconductor substrate; a plurality of memory cell arrays being arranged three-dimensionally on the insulating layer and including a plurality of conductive layers stacked in a first direction that intersects a surface of the semiconductor substrate; and a block insulating layer covering a side surface of one of the plurality of conductive layers. A high permittivity layer is provided between the insulating layer and a lowermost layer of the plurality of conductive layers. A permittivity of the high permittivity layer is much higher than that of the insulating layer.
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公开(公告)号：US10121796B2
公开(公告)日：2018-11-06
申请号：US15264984
申请日：2016-09-14
发明人： Takeshi Sonehara , Masaru Kito
IPC分类号： H01L27/115 , H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L27/11575
摘要： According to embodiments, a semiconductor memory device includes a plurality of control gate electrodes laminated on a substrate. A first semiconductor layer has one end connected to the substrate, has a longitudinal direction in a direction intersecting with the substrate, and is opposed to the plurality of control gate electrodes. An electric charge accumulating layer is positioned between this control gate electrode and the first semiconductor layer. A first contact has one end connected to the substrate and another end connected to a source line. A second contact has one end connected to the substrate and another end connected to a wiring other than the source line. The first contact includes a first silicide layer arranged on the substrate. The second contact includes a second silicide layer arranged on the substrate. The first silicide layer has a higher temperature resistance than the second silicide layer.
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5.发明授权公开(公告)号：US11018150B2
公开(公告)日：2021-05-25
申请号：US16128103
申请日：2018-09-11
发明人： Kotaro Fujii , Yasuhiro Uchiyama , Masaru Kito
IPC分类号： H01L27/1157 , H01L27/11582 , H01L27/11565
摘要： A semiconductor memory device includes a first electrode film, a second electrode film separated from the first electrode film in a first direction, a third electrode film separated from the second electrode film in the first direction, a fourth electrode film separated from the third electrode film in the first direction, and a first and a second semiconductor members extending in the first direction. The second electrode film includes a first conductive portion, an insulating portion, and a second conductive portion arranged along a second direction. The first semiconductor member pierces the first, third and fourth electrode films and the insulating portion of the second electrode film. The second semiconductor member pierces the first, third and fourth electrode films, and the first conductive portion or the second conductive portion of the second electrode film.
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公开(公告)号：US20190006275A1
公开(公告)日：2019-01-03
申请号：US15862665
申请日：2018-01-05
发明人： Shigeki KOBAYASHI , Masaru Kito
IPC分类号： H01L23/528 , H01L27/11582 , H01L27/11556 , H01L21/768
摘要： According to one embodiment, a stacked body includes a plurality of conductive layers stacked with an insulator interposed. The stacked body includes a first stacked portion and a second stacked portion. The second stacked portion includes a plurality of terrace portions arranged in a staircase configuration with level differences in a first direction and a second direction. The second stacked portion includes a conductive portion and a spacer portion. The conductive portion is connected to the conductive layer and is provided in same layer as the conductive layer. The spacer portion is provided in same layer as the conductive layer and the conductive portion. The spacer portion is of a material different from the conductive portion.
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公开(公告)号：US09991276B2
公开(公告)日：2018-06-05
申请号：US15070785
申请日：2016-03-15
发明人： Takeshi Sonehara , Masaru Kito
IPC分类号： H01L27/11 , H01L27/11582
CPC分类号： H01L27/11582 , H01L27/11565 , H01L27/11575
摘要： According to one embodiment, a semiconductor device includes a substrate; a first structure; a second structure; a step; an insulating layer; a first pillar; a second pillar; a first contact portion; and a second contact. The first structure includes a first electrode layer and a first insulator. The first structure has a first terrace on a surface of the first insulator. The second structure includes a second electrode layer and a second insulator. The second structure has a second terrace on a surface of the second insulator. The second contact portion is electrically connected to the second electrode layer via the second terrace. The first contact portion is located between the step and the first pillar. The step is located between the first contact portion and the second pillar.
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公开(公告)号：US09985050B2
公开(公告)日：2018-05-29
申请号：US15664924
申请日：2017-07-31
发明人： Yoshiaki Fukuzumi , Ryota Katsumata , Masaru Kidoh , Masaru Kito , Hiroyasu Tanaka , Yosuke Komori , Megumi Ishiduki , Hideaki Aochi
IPC分类号： H01L27/11 , H01L27/11582 , H01L29/51 , H01L27/11575 , H01L27/11573 , H01L27/105 , G11C16/04 , H01L27/11578 , H01L27/11556 , H01L27/11551
CPC分类号： H01L27/11582 , G11C16/0483 , H01L27/1052 , H01L27/11551 , H01L27/11556 , H01L27/11573 , H01L27/11575 , H01L27/11578 , H01L29/513
摘要： A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.
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公开(公告)号：USRE46809E1
公开(公告)日：2018-04-24
申请号：US15018381
申请日：2016-02-08
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/10 , G11C16/26 , H01L27/11582
摘要： A nonvolatile semiconductor memory device includes: a memory unit; and a control unit. The memory unit includes: first and second memory strings including first and second memory transistors with first and second select gates, respectively; and first and second wirings connected thereto. In a selective erase operation of a selected cell transistor of the first memory transistors, the control unit applies V1 voltage to the first wiring, applies V2 voltage lower than V1 to a selected cell gate of the selected cell transistor, applies V3 voltage not higher than V1 and higher than V2 to a non-selected cell gate of the first memory transistors, applies V1 or V4 voltage not higher than V1 and not lower than V3 to the first select gate, and applies V2 or V4 voltage higher than V2 and not higher than V3 to the second wiring or sets the second wiring in a floating state.
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公开(公告)号：US11195849B2
公开(公告)日：2021-12-07
申请号：US16570067
申请日：2019-09-13
发明人： Yasuhito Yoshimizu , Yuji Setta , Masaru Kito
IPC分类号： H01L27/11582 , H01L23/00 , H01L21/28 , H01L21/02 , H01L27/11573 , H01L25/00 , H01L25/18 , H01L21/225 , H01L21/683
摘要： In one embodiment, a semiconductor device includes a first film including a plurality of electrode layers and a plurality of insulating layers provided alternately in a first direction, and a first semiconductor layer provided in the first film via a charge storage layer and extending in the first direction. The device further includes a first conductive member provided in the first film and extending in the first direction, and a second semiconductor layer provided on the first film to contact the first semiconductor layer. The second semiconductor layer includes a first surface on a side of the first film, and a second surface on an opposite side of the first surface. The second surface is an uneven face protruding towards the first direction.
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