公开(公告)号：US20200234580A1

公开(公告)日：2020-07-23

申请号：US16838164

申请日：2020-04-02

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Marie TAKADA ,  Masanobu SHIRAKAWA

IPC: G08G1/0967 ,  G06K9/00 ,  G06T7/70 ,  G08G1/04 ,  G08G1/01 ,  G08G1/137

Abstract: A driving support system includes a first monitoring device on a first object, the first monitoring device having a first controller, a first camera, and a first display, a second monitoring device on a second object, the second monitoring device having a second controller and a second camera, and a server in communication with the first and second monitoring devices. The first and second controllers are each detect a target in images acquired from the respective first or second camera, calculate target information for the target, and transmit the target information to the server. The server generates list information including the target information from the first and second monitoring devices, and transmits the list information to the first and second monitoring devices. The first controller further generates a map according to the list information received from the server, and displays the map on the first display.

公开(公告)号：US20210110875A1

公开(公告)日：2021-04-15

申请号：US17131400

申请日：2020-12-22

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tsukasa TOKUTOMI ,  Masanobu SHIRAKAWA ,  Marie TAKADA ,  Shohei ASAMI ,  Masamichi FUJIWARA

IPC: G11C16/26 ,  G11C16/04 ,  G06F3/06

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first to fourth word lines and first to fourth memory cells. The controller is configured to issue first and second instructions. The controller is further configured to execute a first operation to obtain a first read voltage based on a threshold distribution of the first memory cell, and a second operation to read data from the second memory cell.

公开(公告)号：US20210104282A1

公开(公告)日：2021-04-08

申请号：US17126649

申请日：2020-12-18

Applicant: Toshiba Memory Corporation

Inventor： Tsukasa TOKUTOMI ,  Masanobu SHIRAKAWA ,  Marie TAKADA

IPC: G11C16/26 ,  G11C16/34 ,  G11C16/04 ,  G11C11/56

Abstract: According to an embodiment, a semiconductor memory, on receiving a first command, applies a voltage within a first range and a voltage within a second range to a word line and reads a first bit from a memory cell, and, on receiving a second command, applies a voltage within a third range to the word line and reads a second bit from the memory cell. The controller issues the first command a plurality of times and changes the voltages to be applied to the word line within the first range and the second range in accordance with the plurality of first commands, specifies a first and second voltage within the first and the second range, respectively, and estimates a third voltage within the third range. The voltage applied to read the second bit is the estimated third voltage.

公开(公告)号：US20210096949A1

公开(公告)日：2021-04-01

申请号：US17092054

申请日：2020-11-06

Applicant: Toshiba Memory Corporation

Inventor： Kengo KUROSE ,  Masanobu SHIRAKAWA ,  Marie TAKADA

IPC: G06F11/10 ,  G11C16/04 ,  G11C11/56 ,  G11C16/26

Abstract: According to an embodiment, a memory controller obtains first data in a first page using a first voltage, obtains a first shift amount based on a first and second number. The first and second numbers represent numbers of bits each of which has different values in a first and second manner between the first data and first expected data. The controller obtains second data in the second page using a second voltage and a second shift amount, and obtains a third shift amount based on a third and fourth number, the third and fourth numbers respectively represent numbers of bits each of which has different values in the first and second manner between the second data and second expected data.

公开(公告)号：US20200301778A1

公开(公告)日：2020-09-24

申请号：US16550355

申请日：2019-08-26

Applicant: Toshiba Memory Corporation

Inventor： Kengo KUROSE ,  Masanobu SHIRAKAWA ,  Marie TAKADA

IPC: G06F11/10 ,  G11C16/04 ,  G11C11/56 ,  G11C16/26

Abstract: According to an embodiment, a memory controller obtains first data in a first page using a first voltage, obtains a first shift amount based on a first and second number. The first and second numbers represent numbers of bits each of which has different values in a first and second manner between the first data and first expected data. The controller obtains second data in the second page using a second voltage and a second shift amount, and obtains a third shift amount based on a third and fourth number, the third and fourth numbers respectively represent numbers of bits each of which has different values in the first and second manner between the second data and second expected data.

公开(公告)号：US20200294610A1

公开(公告)日：2020-09-17

申请号：US16562482

申请日：2019-09-06

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Marie TAKADA ,  Masanobu SHIRAKAWA ,  Yoshihiro UEDA ,  Naomi TAKEDA ,  Hideki YAMADA

IPC: G11C19/08 ,  G11C11/16 ,  G06F3/06

Abstract: According to one embodiment, a magnetic memory puts a first magnetic domain having a magnetization direction which is the same as or opposite to a magnetic domain of a first layer of a magnetic memory line, into the first layer, based on a value of data and the magnetization direction of the first layer. When receiving a first command, the magnetic memory puts a first additional magnetic domain and a second additional magnetic domain having a magnetization direction opposite to the first additional magnetic domain into the magnetic memory line. When receiving a second command, the magnetic memory read the first and second additional magnetic domains to determine the magnetization direction of the first magnetic domain.

公开(公告)号：US20200098431A1

公开(公告)日：2020-03-26

申请号：US16697540

申请日：2019-11-27

Applicant: Toshiba Memory Corporation

Inventor： Masanobu SHIRAKAWA ,  Marie TAKADA ,  Tsukasa TOKUTOMI ,  Yoshihisa KOJIMA ,  Kiichi TACHI

IPC: G11C16/08 ,  G11C16/34 ,  H01L27/1157 ,  G11C16/12 ,  G11C16/04 ,  G11C16/26 ,  G11C11/56 ,  H01L27/11582 ,  G11C16/10

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes: first memory cells, first word lines, a first row decoder, and a driver circuit. The first row decoder includes first transistors capable of coupling the first word lines to first signal lines, and a first block decoder supplying a first block selection signal to the first transistors. When the controller issues a data read command, the first block decoder asserts the first block selection signal to allow the first transistors to transfer a first voltage to a selected first word line, and a second voltage to unselected other first word lines. After data is read, the first block decoder continues asserting the first block selection signal, and the driver circuit transfers a third voltage.

公开(公告)号：US20180190348A1

公开(公告)日：2018-07-05

申请号：US15697737

申请日：2017-09-07

Applicant: Toshiba Memory Corporation

Inventor： Tsukasa TOKUTOMI ,  Masanobu SHIRAKAWA ,  Marie TAKADA

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/26

CPC classification number: G11C11/5642 ,  G06F11/1068 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C16/30 ,  G11C2211/563 ,  G11C2211/5642 ,  H01L27/1157 ,  H01L27/11582

Abstract: According to an embodiment, a control circuitry performing: a first operation of reading data out of a memory cell with a first voltage applied to a word line while changing the first voltage by a first shift amount within a first range, and a second operation of reading data out of the memory cell with a second voltage applied to the word line while changing the second voltage by a second shift amount within a second range, wherein the second shift amount is smaller than the first shift amount, and wherein the control circuitry performs the second operation to apply the second voltage to the word line subsequently to application of the first voltage to the word line in the first operation.

公开(公告)号：US20210110874A1

公开(公告)日：2021-04-15

申请号：US17131026

申请日：2020-12-22

Applicant: Toshiba Memory Corporation

Inventor： Masanobu SHIRAKAWA ,  Tsukasa TOKUTOMI ,  Marie TAKADA

IPC: G11C16/26 ,  G11C11/56 ,  G11C16/04

Abstract: According to one embodiment, a memory system includes a semiconductor memory device and a controller. The device includes a plurality of memory cells capable of storing at least first to third data and a word line coupled to the plurality of memory cells. The first data is determined by a first read operation including a first read level. The second data is determined by a second read operation including a second read level. The third data is determined by a third read operation including a third read level. The controller controls the semiconductor memory device to perform a forth read operation including the first and second read levels in a search operation for first to third read voltages corresponding to the first to third read levels, respectively.

公开(公告)号：US20200303000A1

公开(公告)日：2020-09-24

申请号：US16564279

申请日：2019-09-09

Applicant: Toshiba Memory Corporation

Inventor： Tomonori TAKAHASHI ,  Masanobu SHIRAKAWA ,  Osamu TORII ,  Marie TAKADA

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26

Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell configured to hold 5-bit data; a word line coupled to the memory cell; and a row decoder configured to apply first to 31st voltages to the word line. A first bit of the 5-bit data is established by reading operations using first to sixth voltages. A second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages. A third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages. A fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages. A fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages.