公开(公告)号：US20210040345A1

公开(公告)日：2021-02-11

申请号：US17082259

申请日：2020-10-28

Applicant: Toshiba Memory Corporation

Inventor： Norikatsu SASAO ,  Koji Asakawa ,  Tomoaki Sawabe ,  Shinobu Sugimura

IPC: C09D153/00 ,  C08F20/28 ,  C09D125/06 ,  G03F7/00 ,  C09D133/14 ,  C08F12/08

Abstract: According to one embodiment, a pattern formation method is disclosed. The method includes a preparation process, a block copolymer layer formation process, and a contact process. The preparation process includes preparing a pattern formation material including a block copolymer including a first block and a second block. The first block includes a first main chain and a plurality of first side chains. At least one of the first side chains includes a plurality of carbonyl groups. The block copolymer layer formation process includes forming a block copolymer layer on a first member. The block copolymer layer includes the pattern formation material and includes a first region and a second region. The first region includes the first block. The second region includes the second block. The contact process includes causing the block copolymer layer to contact a metal compound including a metallic element.

公开(公告)号：US20190169461A1

公开(公告)日：2019-06-06

申请号：US16047419

申请日：2018-07-27

Applicant: Toshiba Memory Corporation

Inventor： Norikatsu Sasao ,  Koji Asakawa ,  Tomoaki Sawabe ,  Shinobu Sugimura

IPC: C09D153/00 ,  C08F20/28 ,  C08F12/08 ,  C09D133/14 ,  C09D125/06

Abstract: According to one embodiment, a pattern formation method is disclosed. The method includes a preparation process, a block copolymer layer formation process, and a contact process. The preparation process includes preparing a pattern formation material including a block copolymer including a first block and a second block. The first block includes a first main chain and a plurality of first side chains. At least one of the first side chains includes a plurality of carbonyl groups. The block copolymer layer formation process includes forming a block copolymer layer on a first member. The block copolymer layer includes the pattern formation material and includes a first region and a second region. The first region includes the first block. The second region includes the second block. The contact process includes causing the block copolymer layer to contact a metal compound including a metallic element.

公开(公告)号：US11161999B2

公开(公告)日：2021-11-02

申请号：US17082259

申请日：2020-10-28

Applicant: Toshiba Memory Corporation

Inventor： Norikatsu Sasao ,  Koji Asakawa ,  Tomoaki Sawabe ,  Shinobu Sugimura

IPC: C09D153/00 ,  C08F20/28 ,  C09D125/06 ,  C09D133/14 ,  C08F12/08 ,  G03F7/00 ,  B05D5/00

Abstract: According to one embodiment, a pattern formation method is disclosed. The method includes a preparation process, a block copolymer layer formation process, and a contact process. The preparation process includes preparing a pattern formation material including a block copolymer including a first block and a second block. The first block includes a first main chain and a plurality of first side chains. At least one of the first side chains includes a plurality of carbonyl groups. The block copolymer layer formation process includes forming a block copolymer layer on a first member. The block copolymer layer includes the pattern formation material and includes a first region and a second region. The first region includes the first block. The second region includes the second block. The contact process includes causing the block copolymer layer to contact a metal compound including a metallic element.

公开(公告)号：US10950735B2

公开(公告)日：2021-03-16

申请号：US16351245

申请日：2019-03-12

Applicant: Toshiba Memory Corporation

Inventor： Junji Kataoka ,  Tomomasa Ueda ,  Tomoaki Sawabe ,  Keiji Ikeda ,  Nobuyoshi Saito

IPC: H01L29/786 ,  H01L45/00 ,  H01L29/24

Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer and a first layer. The semiconductor layer includes a first portion including a first element and oxygen. The first element includes at least one selected from the group consisting of In, Ga, Zn, Al, Sn, Ti, Si, Ge, Cu, As, and W. The first layer includes a second element including at least one selected from the group consisting of W, Ti, Ta, Mo, Cu, Al, Ag, Hf, Au, Pt, Pd, Ru, Y, V, Cr, Ni, Nb, In, Ga, Zn, and Sn. The first portion includes a first region and a second region. The second region is provided between the first region and the first layer. The first region includes a bond of the first element and oxygen. The second region includes a bond of the first element and a metallic element.

公开(公告)号：US10790396B2

公开(公告)日：2020-09-29

申请号：US16103880

申请日：2018-08-14

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tomoaki Sawabe ,  Tomomasa Ueda ,  Keiji Ikeda ,  Tsutomu Tezuka ,  Nobuyoshi Saito

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L27/108 ,  H01L29/778 ,  H01L21/44 ,  H01L21/4763

Abstract: A semiconductor device of an embodiment includes a first electrode; a second electrode; an oxide semiconductor layer provided between the first electrode and the second electrode and extending in a first direction; a gate electrode surrounding the oxide semiconductor layer; and a first gate insulating layer provided between the gate electrode and the oxide semiconductor layer, the first gate insulating layer surrounding the oxide semiconductor layer, and the first gate insulating layer having a length in the first direction shorter than a length of the oxide semiconductor layer in the first direction.

公开(公告)号：US20190218321A1

公开(公告)日：2019-07-18

申请号：US16123095

申请日：2018-09-06

Applicant: Toshiba Memory Corporation

Inventor： Ryosuke YAMAMOTO ,  Seiji Morita ,  Norikatsu Sasao ,  Koji Asakawa ,  Tomoaki Sawabe ,  Shinobu Sugimura

IPC: C08F220/08 ,  C08F220/28 ,  C08F220/18 ,  C08F212/08 ,  C08F120/08 ,  C08F120/28 ,  G03F7/00 ,  G03F7/004 ,  G03F7/20

CPC classification number: C08F220/08 ,  C08F120/08 ,  C08F120/28 ,  C08F212/08 ,  C08F220/18 ,  C08F220/28 ,  C08F2220/1808 ,  C08F2220/283 ,  G03F7/0035 ,  G03F7/0047 ,  G03F7/2043

Abstract: A pattern forming material according to an embodiment is a pattern forming material comprising a polymer composed of a plurality of monomer units bonded to each other. Each of the monomer units includes an ester structure having a first carbonyl group and at least one second carbonyl group bonded to the ester structure. A second carbonyl group farthest from a main chain of the polymer constituting the pattern forming material among second carbonyl groups is in a linear chain state.

公开(公告)号：US20190086803A1

公开(公告)日：2019-03-21

申请号：US15916229

申请日：2018-03-08

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Koji Asakawa ,  Seekei Lee ,  Naoko Kihara ,  Norikatsu Sasao ,  Tomoaki Sawabe ,  Shinobu Sugimura

IPC: G03F7/039 ,  G03F7/16 ,  G03F7/20 ,  G03F7/004 ,  G03F7/32 ,  G03F7/038

Abstract: According to one embodiment, a pattern formation method is disclosed. The method can include a film formation process, and a exposure process. The film formation process forms a pattern formation material film on a base body. The pattern formation material film includes a pattern formation material including a first portion and a second portion. The first portion includes at least one of acrylate or methacrylate. The second portion includes an alicyclic compound and a carbonyl group. The alicyclic compound has an ester bond to the at least one of the acrylate or the methacrylate. The carbonyl group is bonded to the alicyclic compound. The exposure process causes the pattern formation material film to expose to a metal compound including a metallic element.

公开(公告)号：US20190084829A1

公开(公告)日：2019-03-21

申请号：US15917053

申请日：2018-03-09

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Norikatsu SASAO ,  Koji Asakawa ,  Seekei Lee ,  Naoko Kihara ,  Tomoaki Sawabe ,  Shinobu Sugimura

IPC: B81C1/00 ,  B32B27/30

Abstract: According to one embodiment, a pattern formation method is disclosed. The method can include a preparation process, a first layer formation process, a block copolymer layer formation process, and a contact process. The preparation process prepares a pattern formation material including a polymer including a first chemical structure including carbon, hydrogen, and a first group. The first group includes one of a vinyl group, a hydroxy group, or a first element. The first layer formation process forms a first layer on a base body. The first layer includes the pattern formation material. The block copolymer layer formation process forms a block copolymer layer on the first layer. The block copolymer layer includes a first polymer and a second polymer. The block copolymer layer formation process includes forming first and second regions. The contact process causes the block copolymer layer to contact a metal compound including a metallic element.

公开(公告)号：US11024719B2

公开(公告)日：2021-06-01

申请号：US16563307

申请日：2019-09-06

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tomoaki Sawabe ,  Nobuyoshi Saito ,  Junji Kataoka ,  Tomomasa Ueda ,  Keiji Ikeda

IPC: H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/49 ,  H01L29/51 ,  H01L27/24 ,  H01L29/78

Abstract: A semiconductor device of an embodiment includes a first electrode, a second electrode, an oxide semiconductor channel, an insulation layer, an oxide layer, and a gate electrode. The oxide semiconductor channel includes a portion extending along a first direction and connects the first electrode to the second electrode. The insulation layer surrounds the oxide semiconductor channel. The oxide layer covers the oxide semiconductor channel and the insulation layer, and includes an oxide of a metal element. The gate electrode covers the oxide semiconductor channel, the insulation layer, and the oxide layer, and includes the metal element.

公开(公告)号：US10553601B2

公开(公告)日：2020-02-04

申请号：US16041460

申请日：2018-07-20

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tsutomu Tezuka ,  Fumitaka Arai ,  Keiji Ikeda ,  Tomomasa Ueda ,  Nobuyoshi Saito ,  Chika Tanaka ,  Kentaro Miura ,  Tomoaki Sawabe

IPC: H01L27/11568 ,  G11C16/04 ,  H01L29/66 ,  G11C5/06 ,  G11C16/26 ,  G11C16/08 ,  G11C16/10 ,  G11C11/56 ,  H01L27/11582 ,  H01L29/792

Abstract: According to one embodiment, a memory includes: a member extending in a first direction and including an oxide semiconductor layer including first to third portions arranged in order from the bit line to the source line; first, second and third conductive layers arranged along the first direction and facing the first to third portions, respectively, the first conductive layer including first material, and each of the second and third conductive layer including a second material different from the first material; a memory cell in a first position corresponding to the first portion, the memory cell including a charge storage layer in the oxide semiconductor layer; a first transistor in a second position corresponding to the second portion; and a second transistor in a third position corresponding to the third portion.