公开(公告)号：US20170373082A1

公开(公告)日：2017-12-28

申请号：US15682996

申请日：2017-08-22

Applicant: Toshiba Memory Corporation

Inventor： Katsuyuki SEKINE ,  Tatsuya KATO ,  Fumitaka ARAI ,  Toshiyuki IWAMOTO ,  Yuta WATANABE ,  Wataru SAKAMOTO ,  Hiroshi ITOKAWA ,  Akio KANEKO

IPC: H01L27/11556 ,  H01L21/768 ,  H01L29/51 ,  H01L29/788 ,  H01L29/423 ,  H01L21/02 ,  H01L21/28 ,  H01L29/45 ,  H01L29/49 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/285 ,  H01L27/11519 ,  H01L29/10

CPC classification number: H01L27/11556 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02181 ,  H01L21/02271 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76801 ,  H01L27/11519 ,  H01L29/1037 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/456 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/515 ,  H01L29/517 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7883 ,  H01L29/7889

Abstract: A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the semiconductor pillar and the second electrode, a second insulating film provided between the first electrode and the second electrode and on two first-direction sides of the first electrode, and a conductive film provided between the second electrode and the second insulating film, the conductive film not contacting the first insulating film.

公开(公告)号：US20190386018A1

公开(公告)日：2019-12-19

申请号：US16294982

申请日：2019-03-07

Applicant: Toshiba Memory Corporation

Inventor： Yuta WATANABE ,  Akira Mino ,  Masahisa Sonoda ,  Takashi Shimizu

IPC: H01L27/11578 ,  H01L27/11568 ,  H01L27/11521 ,  H01L27/11551

Abstract: A semiconductor memory device of embodiments includes a semiconductor substrate having a first and a second region adjacent to the first region in a first direction, a laminated body including electrode layers laminated on the semiconductor substrate in a second direction, a first insulator splitting the laminated body at the second region in a third direction, and extending in the first and second direction, and branching into two insulator films at the first region, and enclosing continuously a first portion of the laminated body, a contact portion extending in the first portion in the second direction, and a memory portion extending through the laminated body and the first insulator in the second direction at the second region. A first width in the third direction of the first portion is wider than a second width in the third direction of at least one of the electrode layers at the second region.

公开(公告)号：US20170352672A1

公开(公告)日：2017-12-07

申请号：US15686292

申请日：2017-08-25

Applicant: Toshiba Memory Corporation

Inventor： Wataru SAKAMOTO ,  Tatsuya KATO ,  Yuta WATANABE ,  Katsuyuki SEKINE ,  Toshiyuki IWAMOTO ,  Fumitaka ARAI

IPC: H01L27/11556 ,  H01L23/528

CPC classification number: H01L27/11556 ,  H01L23/528 ,  H01L27/11521

Abstract: A semiconductor memory device according to an embodiment includes first and second semiconductor pillars extending in a first direction and being arranged along a second direction, first and second interconnects extending in a third direction and being provided between the first semiconductor pillar and the second semiconductor pillar, a first electrode provided between the first semiconductor pillar and the first interconnect, a second electrode provided between the second semiconductor pillar and the second interconnect, third and fourth interconnects extending in the second direction, a first contact contacting the first semiconductor pillar and being connected to the third interconnect, and a second contact contacting the second semiconductor pillar and being connected to the fourth interconnect. The third and fourth interconnects each pass through both a region directly above the first semiconductor pillar and a region directly above the second semiconductor pillar.