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    Vertical dual gate field effect transistor
    1.
    发明授权
    Vertical dual gate field effect transistor 失效
    垂直双栅场效应晶体管

    公开(公告)号：US07176089B2

    公开(公告)日：2007-02-13

    申请号：US10853177

    申请日：2004-05-26

    申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  James M. Leas ,  William H-L Ma ,  Paul A. Rabidoux

    发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  James M. Leas ,  William H-L Ma ,  Paul A. Rabidoux

    IPC分类号： H01L21/336

    CPC分类号： H01L29/78642 ,  H01L21/2255 ,  H01L21/76897 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7831

    摘要： A method of manufacturing provides a vertical transistor particularly suitable for high density integration and which includes potentially independent gate structures on opposite sides of a semiconductor pillar formed by etching or epitaxial growth in a trench. The gate structure is surrounded by insulating material which is selectively etchable to isolation material surrounding the transistor. A contact is made to the lower end of the pillar (e.g. the transistor drain) by selectively etching the isolation material selective to the insulating material. The upper end of the pillar is covered by a cap and sidewalls of selectively etchable materials so that gate and source connection openings can also be made by selective etching with good registration tolerance. A dimension of the pillar in a direction parallel to the chip surface is defined by a distance between isolation regions and selective etching and height of the pillar is defined by thickness of a sacrificial layer.

    摘要翻译： 一种制造方法提供特别适用于高密度积分的垂直晶体管，其包括通过在沟槽中蚀刻或外延生长而形成的半导体柱的相对侧上的潜在独立栅极结构。 栅极结构被绝缘材料包围，绝缘材料可选择性地蚀刻到围绕晶体管的隔离材料。 通过选择性地蚀刻对绝缘材料有选择性的隔离材料，对柱的下端（例如，晶体管漏极）进行接触。 柱的上端由盖​​和可选择性蚀刻材料的侧壁覆盖，使得栅极和源极连接开口也可以通过具有良好配准公差的选择性蚀刻制成。 在平行于芯片表面的方向上的柱的尺寸由隔离区域和选择性蚀刻之间的距离限定，并且柱的高度由牺牲层的厚度限定。

    Method using disposable and permanent films for diffusion and implant doping
    2.
    发明授权
    Method using disposable and permanent films for diffusion and implant doping 失效
    使用一次性和永久性膜进行扩散和注入掺杂的方法

    公开(公告)号：US06506653B1

    公开(公告)日：2003-01-14

    申请号：US09524677

    申请日：2000-03-13

    申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  William H-L Ma ,  Patricia M. Marmillion ,  Donald W. Rakowski

    发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  William H-L Ma ,  Patricia M. Marmillion ,  Donald W. Rakowski

    IPC分类号： H01L21336

    CPC分类号： H01L29/6659 ,  H01L21/2254 ,  H01L21/2255 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/665

    摘要： Methods are provided that use disposable and permanent films to dope underlying layers through diffusion. Additionally, methods are provided that use disposable films during implantation doping and that provide a surface from which to dope underlying materials. Some of these disposable films can be created from a traditionally non-disposable film and made disposable. In this manner, solvents may be used that do not etch underlying layers of silicon-based materials. Preferably, deep implantation is performed to form source/drain regions, then an anneal step is performed to activate the dopants. A conformal layer is deposited and implanted with dopants. One or more anneal steps are performed to create very shallow extensions in the source/drain regions.

    摘要翻译： 提供了使用一次性和永久性膜通过扩散来掺杂下层的方法。 此外，提供了在植入掺杂期间使用一次性膜的方法，并且提供了用于涂覆下层材料的表面。 这些一次性膜中的一些可以由传统的非一次性膜制成并制成一次性的。 以这种方式，可以使用不蚀刻硅基材料的下层的溶剂。 优选地，进行深度注入以形成源极/漏极区域，然后执行退火步骤以激活掺杂剂。 沉积保形层并用掺杂剂注入。 执行一个或多个退火步骤以在源极/漏极区域中产生非常浅的延伸。

    Method for etching a semiconductor substrate using germanium hard mask
    3.
    发明授权
    Method for etching a semiconductor substrate using germanium hard mask 失效
    使用锗硬掩模蚀刻半导体衬底的方法

    公开(公告)号：US06867143B1

    公开(公告)日：2005-03-15

    申请号：US09599783

    申请日：2000-06-22

    申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  William H-L. Ma

    发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  William H-L. Ma

    IPC分类号： C23F4/00 ,  C23G1/00 ,  H01L21/302 ,  H01L21/308 ,  H01L21/3213

    CPC分类号： H01L21/3081 ,  C23F4/00 ,  C23G1/00 ,  H01L21/3086 ,  H01L21/32134

    摘要： An etching process using germanium hard mask (25) includes forming a dielectric layer (15) over a major surface (11) of a semiconductor substrate (10) and depositing a metallic germanium layer (22) over the dielectric layer (15). The metallic germanium layer (22) is patterned through a photo resist (24) to form the germanium hard mask (25). The dielectric layer (15) is selectively etched through the germanium hard mask (25) to form a dielectric hard mask (35), through which the semiconductor substrate (10) is subsequently etched. After forming the dielectric hard mask (35), the germanium hard mask (25) is stripped away by oxidizing the metallic germanium hard mask (25) to transform it into a layer (27) of germanium oxide and rinsing the semiconductor substrate (10) in water to remove the germanium oxide layer (27). Preferably, the germanium hard mask (25) is removed before etching the semiconductor substrate (10).

    摘要翻译： 使用锗硬掩模（25）的蚀刻工艺包括在半导体衬底（10）的主表面（11）上形成电介质层（15），并在电介质层（15）上沉积金属锗层（22）。 通过光致抗蚀剂（24）将金属锗层（22）图案化以形成锗硬掩模（25）。 通过锗硬掩模（25）选择性地蚀刻电介质层（15）以形成电介质硬掩模（35），随后蚀刻半导体衬底（10）。 在形成电介质硬掩模（35）之后，通过氧化金属锗硬掩模（25）将锗硬掩模（25）剥离，将其转化成氧化锗层（27）并冲洗半导体衬底（10）， 在水中以除去氧化锗层（27）。 优选地，在蚀刻半导体衬底（10）之前去除锗硬掩模（25）。

    Method of making differently sized vias and lines on the same lithography level
    4.
    发明授权
    Method of making differently sized vias and lines on the same lithography level 失效
    在相同光刻级别上制作不同尺寸的通孔和线的方法

    公开(公告)号：US06444402B1

    公开(公告)日：2002-09-03

    申请号：US09532187

    申请日：2000-03-21

    申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  William H-L. Ma

    发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  William H-L. Ma

    IPC分类号： G03C500

    CPC分类号： H01L21/31144 ,  G03F7/0035 ,  G03F7/40 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/76816

    摘要： Features of two or more distinct sizes designed to optimize performance of an integrated circuit device are formed by transferring a pattern from a resist patterned with features of a single minimum feature size for which a resist exposure tool is optimized to a layer of preferably soluble material such as germanium oxide. Portions of this pattern are then enlarged using a block-out mask and the resulting pattern transferred to a further underlying layer preferably using an anisotropic reactive ion etch. The soluble material can then be removed leaving a robust mask with differing feature sizes for further processing. Preferably, Damascene conductive lines and vias are formed by providing an insulator as the further underlying material and filling the openings with metal or other conductive material.

    摘要翻译： 设计用于优化集成电路器件性能的两个或多个不同尺寸的特征通过将图案从具有抗蚀剂曝光工具优化的单个最小特征尺寸的特征的抗蚀剂转移到优选可溶性材料层而形成， 作为氧化锗。 然后使用阻挡掩模将该图案的部分放大，并且将所得到的图案优选地使用各向异性反应离子蚀刻转移到另一下层。 然后可以去除可溶性材料，留下具有不同特征尺寸的坚固的掩模，用于进一步处理。 优选地，通过提供绝缘体作为其他下层材料并用金属或其它导电材料填充开口来形成镶嵌导电线和通孔。

    Vertical dual gate field effect transistor
    6.
    发明授权
    Vertical dual gate field effect transistor 有权
    垂直双栅场效应晶体管

    公开(公告)号：US06798017B2

    公开(公告)日：2004-09-28

    申请号：US09944665

    申请日：2001-08-31

    申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  James M. Leas ,  William H-L Ma ,  Paul A. Rabidoux

    发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  James M. Leas ,  William H-L Ma ,  Paul A. Rabidoux

    IPC分类号： H01L2976

    CPC分类号： H01L29/78642 ,  H01L21/2255 ,  H01L21/76897 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7831

    摘要： A vertical transistor particularly suitable for high density integration includes potentially independent gate structures on opposite sides of a semiconductor pillar formed by etching or epitaxial growth in a trench. The gate structure is surrounded by insulating material which is selectively etchable to isolation material surrounding the transistor. A contact is made to the lower end of the pillar (e.g. the transistor drain) by selectively etching the isolation material selective to the insulating material. The upper end of the pillar is covered by a cap and sidewalls of selectively etchable materials so that gate and source connection openings can also be made by selective etching with good registration tolerance. A dimension of the pillar in a direction parallel to the chip surface is defined by a distance between isolation regions and selective etching and height of the pillar is defined by thickness of a sacrificial layer.

    摘要翻译： 特别适用于高密度集成的垂直晶体管包括通过在沟槽中蚀刻或外延生长形成的半导体柱的相对侧上的潜在的独立栅极结构。 栅极结构被绝缘材料包围，绝缘材料可选择性地蚀刻到围绕晶体管的隔离材料。 通过选择性地蚀刻对绝缘材料有选择性的隔离材料，对柱的下端（例如，晶体管漏极）进行接触。 柱的上端由盖​​和可选择性蚀刻材料的侧壁覆盖，使得栅极和源极连接开口也可以通过具有良好配准公差的选择性蚀刻制成。 在平行于芯片表面的方向上的柱的尺寸由隔离区域和选择性蚀刻之间的距离限定，并且柱的高度由牺牲层的厚度限定。

    Implantation of gate regions in semiconductor device fabrication
    9.
    发明授权
    Implantation of gate regions in semiconductor device fabrication 失效
    在半导体器件制造中植入栅极区域

    公开(公告)号：US07557023B2

    公开(公告)日：2009-07-07

    申请号：US11532189

    申请日：2006-09-15

    申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

    发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

    IPC分类号： H01L21/425

    CPC分类号： H01L29/66545 ,  H01L21/0273 ,  H01L21/266 ,  H01L21/28035 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/6659

    摘要： A semiconductor fabrication method. The method includes providing a semiconductor structure which includes (i) a semiconductor layer, (ii) a gate dielectric layer on the semiconductor layer, and (iii) a gate electrode region on the gate dielectric layer. The gate dielectric layer is sandwiched between and electrically insulates the semiconductor layer and the gate electrode region. The semiconductor layer and the gate dielectric layer share a common interfacing surface which defines a reference direction perpendicular to the common interfacing surface and pointing from the semiconductor layer to the gate dielectric layer. Next, a resist layer is formed on the gate dielectric layer and the gate electrode region. Next, a cap portion of the resist layer directly above the gate electrode region in the reference direction is removed without removing any portion of the resist layer not directly above the gate electrode region in the reference direction.

    摘要翻译： 半导体制造方法。 该方法包括提供半导体结构，其包括（i）半导体层，（ii）半导体层上的栅极电介质层，以及（iii）栅极电介质层上的栅电极区。 栅极电介质层被夹在半导体层和栅极电极区域之间并使其电绝缘。 半导体层和栅极介电层共享公共接口表面，其界定垂直于公共接口表面的参考方向并且从半导体层指向栅极介电层。 接下来，在栅极电介质层和栅极电极区域上形成抗蚀剂层。 接下来，去除在参考方向上正好在栅极区域上方的抗蚀剂层的盖部分，而不去除在参考方向上不在栅电极区域正上方的任何部分的抗蚀剂层。