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    Semiconductor memory device
    1.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US4942556A

    公开(公告)日：1990-07-17

    申请号：US377181

    申请日：1989-07-10

    申请人： Toshio Sasaki ,  Masakazu Aoki ,  Masashi Horiguchi ,  Yoshinobu Nakagome ,  Shinichi Ikenaga ,  Toshiaki Masuhara

    发明人： Toshio Sasaki ,  Masakazu Aoki ,  Masashi Horiguchi ,  Yoshinobu Nakagome ,  Shinichi Ikenaga ,  Toshiaki Masuhara

    IPC分类号： G11C15/04 ,  G11C29/00 ,  G11C29/44

    CPC分类号： G11C29/76 ,  G11C15/04 ,  G11C15/046 ,  G11C29/44

    摘要： In a defect relieving technology which replaces defective memory cells of a semiconductor memory device by spare memory cells, use is made of an associative memory. Address information of a defective memory cell is stored as a reference data of the associative memory, and new address information of a spare memory cell is written down as output data of the associative memory. A variety of improvements are made to the associative memory. For instance, a plurality of coincidence detection signal lines of the associative memory are divided into at least two groups, and one group among them is selected by switching means. Reference data of the associative memory comprises three values consisting of binary information of "0" and "1", and don't care value "X". The associative memory further includes a plurality of electrically programable non-volatile semiconductor memory elements.

    摘要翻译： 在通过备用存储器单元代替半导体存储器件的缺陷存储单元的缺陷解除技术中，使用关联存储器。 存储有缺陷的存储单元的地址信息被存储为关联存储器的参考数据，并且备用存储单元的新地址信息被写入作为关联存储器的输出数据。 对联想记忆进行了各种改进。 例如，关联存储器的多个符合检测信号线被划分为至少两组，其中一组由切换装置选择。 关联存储器的参考数据包括由“0”和“1”的二进制信息组成的三个值，并且不关心值“X”。 关联存储器还包括多个可电可编程的非易失性半导体存储器元件。

    Semiconductor memory for serial data access
    2.
    发明授权
    Semiconductor memory for serial data access 失效
    用于串行数据访问的半导体存储器

    公开(公告)号：US4701884A

    公开(公告)日：1987-10-20

    申请号：US896257

    申请日：1986-08-14

    申请人： Masakazu Aoki ,  Masashi Horiguchi ,  Yoshinobu Nakagome ,  Shinichi Ikenaga ,  Katsuhiro Shimohigashi ,  Toshiaki Masuhara ,  Kiyoo Itoh ,  Hideo Nakamura ,  Osamu Minato

    发明人： Masakazu Aoki ,  Masashi Horiguchi ,  Yoshinobu Nakagome ,  Shinichi Ikenaga ,  Katsuhiro Shimohigashi ,  Toshiaki Masuhara ,  Kiyoo Itoh ,  Hideo Nakamura ,  Osamu Minato

    IPC分类号： G11C11/56 ,  H01L27/108 ,  G11C13/00

    CPC分类号： G11C11/565 ,  H01L27/10805

    摘要： A semiconductor memory device is proposed wherein at least an array comprising a plurality of memory cells each having at least one capacity, a select mechanism for specifying the position of each memory cell, data lines connected to said memory cells for transmitting the data and a data writing and a data reading mechanisms are provided. The feature of this device lies in that the voltage generator for serially generating three or more values of the voltage which are different from each other and the means for applying said voltage to said memory cells are provided on the same semiconductor board as the same said memory cells, and as the said reading mechanism the column register is provided which, as said reading mechanism, has the mechanism for deciding the data, transfer gate which is provided between said deciding means and said data line, and the bias charge transfer mechanism which is provided between said transfer gate and said deciding mechanism, and having at least two or more memory elements for temporarily storing said decided data.

    摘要翻译： 提出了一种半导体存储器件，其中至少包括多个具有至少一个容量的存储单元的阵列，用于指定每个存储单元的位置的选择机构，连接到所述存储器单元的用于发送数据的数据线和数据 提供写入和数据读取机制。 该装置的特征在于，用于串联产生彼此不同的三个或更多个电压值的电压发生器和用于将所述电压施加到所述存储单元的装置设置在与所述存储器相同的半导体板上 并且作为所述读取机构，列寄存器被提供，其作为所述读取机构具有用于确定数据的机制，所述决定装置和所述数据线之间提供的传送门和作为所述读取机构的偏置电荷传送机构 提供在所述传送门和所述判定机构之间，并且具有用于临时存储所述决定的数据的至少两个或更多个存储器元件。

    Semiconductor memory having error correcting means
    4.
    发明授权
    Semiconductor memory having error correcting means 失效
    具有误差校正装置的半导体存储器

    公开(公告)号：US4726021A

    公开(公告)日：1988-02-16

    申请号：US853230

    申请日：1986-04-17

    申请人： Masashi Horiguchi ,  Masakazu Aoki ,  Yoshinobu Nakagome ,  Shinichi Ikenaga ,  Katsuhiro Shimohigashi

    发明人： Masashi Horiguchi ,  Masakazu Aoki ,  Yoshinobu Nakagome ,  Shinichi Ikenaga ,  Katsuhiro Shimohigashi

    IPC分类号： G06F11/10 ,  G11C29/24 ,  G01R31/28

    CPC分类号： G06F11/1008 ,  G06F11/1076 ,  G11C29/24

    摘要： A semiconductor memory having an error correcting function is provided, which has a device by which the user finds no difficulty in making use of the semiconductor memory and can test it with ease. In the semiconductor memory, a signal indicative of the completion of the preparation for reading/writing is outputted from the memory so that the user, after detecting the output of this signal, performs reading/writing data. To facilitate tests, such as a memory cell test for a redundant bit (check bit), an encoding circuit test and a decoding circuit test, the present invention provides that the arranged tests can be made independently of each other.

    摘要翻译： 提供了具有纠错功能的半导体存储器，其具有用户不用利用半导体存储器并且可以容易地进行测试的装置。 在半导体存储器中，从存储器输出表示完成读/写准备的信号，使得用户在检测到该信号的输出之后，执行读/写数据。 为了便于诸如用于冗余位（校验位）的存储器单元测试，编码电路测试和解码电路测试的测试，本发明提供了可以彼此独立地进行布置的测试。

    Semiconductor memory having multiple level storage structure
    5.
    发明授权
    Semiconductor memory having multiple level storage structure 失效
    具有多级存储结构的半导体存储器

    公开(公告)号：US4661929A

    公开(公告)日：1987-04-28

    申请号：US686018

    申请日：1984-12-24

    申请人： Masakazu Aoki ,  Yoshinobu Nakagome ,  Masashi Horiguchi ,  Shinichi Ikenaga ,  Katsuhiro Shimohigashi

    发明人： Masakazu Aoki ,  Yoshinobu Nakagome ,  Masashi Horiguchi ,  Shinichi Ikenaga ,  Katsuhiro Shimohigashi

    IPC分类号： G06F11/10 ,  G11C7/06 ,  G11C11/4091 ,  G11C11/56 ,  G11C11/40

    CPC分类号： G11C11/565 ,  G11C11/4091 ,  G11C7/065 ,  G06F11/1072 ,  G11C29/00 ,  G11C7/06

    摘要： In a semiconductor memory includes a memory array consisting of a plurality of memory cells respectively having at least one storage capacitor, an addressing circuit which designates location of each memory cell, data lines which transmit data connected to said memory cells and data writing and reading circuits connected to said data lines. The semiconductor memory has a multiple level storage structure. In particular, the memory includes an arrangement for sequentially applying, on a time series basis, different voltages of at least 3 levels or more to the gate of a switching MOS transistor of said memory cells, a bias charge supplying means as said data reading circuit and a column register providing at least two or more storage cells which temporarily store said data.

    摘要翻译： 在半导体存储器中，包括由分别具有至少一个存储电容器的多个存储器单元组成的存储器阵列，指定每个存储单元的位置的寻址电路，发送连接到所述存储单元的数据的数据线和数据写入和读取电路 连接到所述数据线。 半导体存储器具有多级存储结构。 具体而言，该存储器包括用于按时间序列依次将至少3级以上的不同电压施加到所述存储单元的开关型MOS晶体管的栅极的装置，作为所述数据读取电路的偏置电荷供给装置 以及提供临时存储所述数据的至少两个或更多个存储单元的列寄存器。

    Sense circuit and semiconductor memory having a current-voltage converter circuit
    6.
    发明授权
    Sense circuit and semiconductor memory having a current-voltage converter circuit 失效
    检测电路和具有电流 - 电压转换器电路的半导体存储器

    公开(公告)号：US4949306A

    公开(公告)日：1990-08-14

    申请号：US201015

    申请日：1988-06-01

    申请人： Yoshinobu Nakagome ,  Masakazu Aoki ,  Masashi Horiguchi ,  Kiyoo Itoh ,  Shinichi Ikenaga

    发明人： Yoshinobu Nakagome ,  Masakazu Aoki ,  Masashi Horiguchi ,  Kiyoo Itoh ,  Shinichi Ikenaga

    IPC分类号： G11C7/06 ,  G11C7/10

    CPC分类号： G11C7/1048 ,  G11C7/062

    摘要： A highly integrated memory features increased reading speed and writing speed. A sense circuit for this memory including a memory cell array having a plurality of memory cells each of which including at least one insulated gate field effect transistor, and a plurality of data lines to which the memory cells are connected. The memory also includes an address selection mechanism which is capable of selecting a memory cell out of a plurality of memory cells and connecting it to the data line. A sense amplifier a mechanism which is connected to the data line and amplifies a voltage according to the data of a memory cell. A common line (input/output line) is connected to the data lines, via a column switch, where the selection depends upon a column address. A main amplifier is connected to the common line (input/output line), and has at least a mechanism for stabilizing the voltage of the common line (input/output line) and an amplifying mechanism.

    摘要翻译： 高度集成的内存具有更高的读取速度和写入速度。 一种用于该存储器的感测电路，包括具有多个存储单元的存储单元阵列，每个存储单元包括至少一个绝缘栅场效应晶体管和存储单元连接到的多条数据线。 存储器还包括地址选择机制，其能够从多个存储器单元中选择存储单元并将其连接到数据线。 读出放大器，连接到数据线并根据存储单元的数据放大电压的机构。 公共线路（输入/输出线路）通过列开关连接到数据线，其中选择取决于列地址。 主放大器连接到公共线（输入/输出线），并且至少具有用于稳定公共线（输入/输出线）的电压和放大机构的机构。

    Ferroelectric memory
    7.
    发明授权
    Ferroelectric memory 失效
    铁电存储器

    公开(公告)号：US5539279A

    公开(公告)日：1996-07-23

    申请号：US362239

    申请日：1994-12-22

    申请人： Kan Takeuchi ,  Masashi Horiguchi ,  Masakazu Aoki ,  Katsumi Matsuno ,  Takeshi Sakata ,  Jun Etoh ,  Yoshinobu Nakagome

    发明人： Kan Takeuchi ,  Masashi Horiguchi ,  Masakazu Aoki ,  Katsumi Matsuno ,  Takeshi Sakata ,  Jun Etoh ,  Yoshinobu Nakagome

    IPC分类号： G11C11/22

    CPC分类号： G11C11/22

    摘要： A highly reliable and high speed ferroelectric memory having a high degree of integration. In a ferroelectric memory having a multiple of memory cells M1, each constituted by one transistor and one ferroelectric capacitor, in the normal operation, the ferroelectric memory is used as a volatile memory in which a voltage on a storage node ST1 stores information in a DRAM mode. Both the electric potential at the plate PL1 of the ferroelectric capacitor and a precharge electric potential on a data line DL1(j) are Vcc/2. When the a power supply voltage is turned on, a polarization state is detected as a ferroelectric memory of a plate electric potential of Vcc/2 and a precharge electric potential of Vss (or Vcc) and the read operation is performed a FERAM mode. The switching between the DRAM mode and the FERAM mode is executed by generating a signal to designate the FERAM mode in the memory along with the turn-on of the power supply and by generating a signal to designate the DRAM mode after completion of the conversion operation from nonvolatile information to volatile information.

    摘要翻译： 具有高度集成度的高可靠性和高速铁电存储器。 在具有由一个晶体管和一个铁电电容器构成的多个存储单元M1的铁电存储器中，在正常操作中，铁电存储器用作其中存储节点ST1上的电压将信息存储在DRAM中的易失性存储器 模式。 强电介质电容器的板PL1的电位和数据线DL1（j）的预充电电位都为Vcc / 2。 当电源电压接通时，偏振状态被检测为Vcc / 2的电位电压和Vss（或Vcc）的预充电电位的铁电存储器，并且读取操作被执行FERAM模式。 DRAM模式和FERAM模式之间的切换通过产生一个信号来指示存储器中的FERAM模式以及电源的导通，并且在完成转换操作之后产生指定DRAM模式的信号 从非易失性信息到易失性信息。

    Voltage converter of semiconductor device
    9.
    发明授权
    Voltage converter of semiconductor device 失效
    半导体器件的电压转换器

    公开(公告)号：US5272393A

    公开(公告)日：1993-12-21

    申请号：US790065

    申请日：1991-11-12

    申请人： Masashi Horiguchi ,  Ryoichi Hori ,  Kiyoo Itoh ,  Yoshinobu Nakagome ,  Masakazu Aoki ,  Hitoshi Tanaka

    发明人： Masashi Horiguchi ,  Ryoichi Hori ,  Kiyoo Itoh ,  Yoshinobu Nakagome ,  Masakazu Aoki ,  Hitoshi Tanaka

    IPC分类号： G05F1/46 ,  H03K17/693 ,  H03K3/01 ,  H03K5/22

    CPC分类号： H03K17/693 ,  G05F1/465

    摘要： In a voltage converter provided in a semiconductor device and supplying an internal supply voltage to a circuit in the semiconductor device, a circuit is provided for generating a first voltage whose dependency on an external supply voltage is regulated to a predetermined small value, while another circuit is provided for generating a second voltage whose dependency on the external supplying voltage is larger than the dependency of the first voltage. Another circuit selects the first voltage when the semiconductor device is in a state of a standard operation and selects the second voltage when the device is in another state of operation, such as testing or aging. The selected voltage may be converted by a differential amplifier which is constituted by a load of P-channel MOS transistors and a source-coupled pair of N-channel MOS transistors. An output of the differential amplifier is fed back through a directly coupled voltage lowering circuit which generates the converted output.

    摘要翻译： 在设置在半导体器件中的电压转换器中并向半导体器件中的电路提供内部电源电压的电路，用于产生对外部电源电压的依赖性被调节到预定的小值的第一电压，而另一个电路 被提供用于产生对外部供电电压的依赖性大于第一电压的依赖性的第二电压。 当半导体器件处于标准操作状态时，另一个电路选择第一电压，并且当器件处于另一种操作状态（例如测试或老化）时选择第二电压。 所选择的电压可以由由P沟道MOS晶体管的负载和源极耦合的N沟道MOS晶体管对构成的差分放大器来转换。 差分放大器的输出通过直接耦合的降压电路反馈，该电路产生转换的输出。