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    Nonvolatile semiconductor storage device and method of manufacture thereof
    3.
    发明授权
    Nonvolatile semiconductor storage device and method of manufacture thereof 有权
    非易失性半导体存储装置及其制造方法

    公开(公告)号：US08222687B2

    公开(公告)日：2012-07-17

    申请号：US12565056

    申请日：2009-09-23

    申请人： Toshitake Yaegashi

    发明人： Toshitake Yaegashi

    IPC分类号： H01L29/788 ,  H01L21/336

    CPC分类号： H01L27/11563 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/517 ,  H01L29/792

    摘要： A nonvolatile semiconductor storage device including a number of memory cells formed on a semiconductor substrate, each of the memory cells has a tunnel insulating film, a charge storage layer, a block insulating film, and a gate electrode which are formed in sequence on the substrate. The gate electrode is structured such that at least first and second gate electrode layers are stacked. The dimension in the direction of gate length of the second gate electrode layer, which is formed on the first gate electrode layer, is smaller than the dimension in the direction of gate length of the first gate electrode layer.

    摘要翻译： 一种非易失性半导体存储器件，包括形成在半导体衬底上的多个存储单元，每个存储单元具有在衬底上依次形成的隧道绝缘膜，电荷存储层，块绝缘膜和栅极电极 。 栅电极被构造成使得至少第一和第二栅极电极层被堆叠。 形成在第一栅极电极层上的第二栅极电极层的栅极长度方向上的尺寸小于第一栅电极层的栅极长度方向的尺寸。

    METHOD OF MANUFACTURING A NON-VOLATILE NAND MEMORY SEMICONDUCTOR INTEGRATED CIRCUIT
    4.
    发明申请
    METHOD OF MANUFACTURING A NON-VOLATILE NAND MEMORY SEMICONDUCTOR INTEGRATED CIRCUIT 有权

    公开(公告)号：US20110248330A1

    公开(公告)日：2011-10-13

    申请号：US13164950

    申请日：2011-06-21

    申请人： Toshitake Yaegashi ,  Yoshio Ozawa

    发明人： Toshitake Yaegashi ,  Yoshio Ozawa

    IPC分类号： H01L27/105 ,  H01L29/788

    CPC分类号： H01L27/115 ,  H01L27/11521

    摘要： A semiconductor integrated circuit device includes first, second gate electrodes, first, second diffusion layers, contact electrodes electrically connected to the first diffusion layers, a first insulating film which has concave portions between the first and second gate electrodes and does not contain nitrogen as a main component, a second insulating film which is formed on the first insulating film and does not contain nitrogen as a main component, and a third insulating film formed on the first diffusion layers, first gate electrodes, second diffusion layers and second gate electrodes with the second insulating film disposed therebetween in a partial region. The second insulating film is formed to fill the concave portions and a portion between the first and second gate electrodes has a multi-layered structure containing at least the first and second insulating films.

    Non-volatile semiconductor memory device and its manufacturing method
    7.
    发明授权
    Non-volatile semiconductor memory device and its manufacturing method 有权
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US07888728B2

    公开(公告)日：2011-02-15

    申请号：US12140946

    申请日：2008-06-17

    申请人： Toshitake Yaegashi ,  Kazuhiro Shimizu ,  Seiichi Aritome

    发明人： Toshitake Yaegashi ,  Kazuhiro Shimizu ,  Seiichi Aritome

    IPC分类号： H01L29/788

    CPC分类号： H01L29/788 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/0483 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11546 ,  Y10S257/908

    摘要： In a non-volatile semiconductor memory device and a method for manufacturing the device, each memory cell and its select Tr have the same gate insulating film as a Vcc Tr. Further, the gate electrodes of a Vpp Tr and Vcc Tr are realized by the use of a first polysilicon layer. A material such as salicide or a metal, which differs from second polysilicon (which forms a control gate layer), may be provided on the first polysilicon layer. With the above features, a non-volatile semiconductor memory device can be manufactured by reduced steps and be operated at high speed in a reliable manner.

    摘要翻译： 在非易失性半导体存储器件及其制造方法中，每个存储单元及其选择Tr具有与Vcc Tr相同的栅极绝缘膜。 此外，Vpp Tr和Vcc Tr的栅极通过使用第一多晶硅层来实现。 可以在第一多晶硅层上提供与第二多晶硅（形成控制栅极层）不同的诸如硅化物或金属的材料。 利用上述特征，可以通过减小的步骤制造非易失性半导体存储器件并以可靠的方式高速运行。

    Non-volatile semiconductor memory device and method of manufacturing the same
    8.
    发明授权
    Non-volatile semiconductor memory device and method of manufacturing the same 失效
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US07737508B2

    公开(公告)日：2010-06-15

    申请号：US11857934

    申请日：2007-09-19

    申请人： Toshitake Yaegashi

    发明人： Toshitake Yaegashi

    IPC分类号： H01L27/105

    CPC分类号： H01L27/11521 ,  H01L21/26513 ,  H01L21/26586 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L29/0847 ,  H01L29/42324 ,  H01L29/6659

    摘要： A non-volatile semiconductor memory device is disclosed, which comprises a memory cell unit including at least one memory cell transistor formed on a semiconductor substrate and having a laminated structure of a charge accumulation layer and a control gate layer, and a selection gate transistor one of the source/drain diffusion layer regions of which is connected to a bit line or a source line and the other of the source/drain diffusion layer regions of which is connected to the memory cell unit. The shape of the source diffusion layer region of the selection gate transistor is asymmetrical to the shape of the drain diffusion layer region thereof below the selection gate transistor.

    摘要翻译： 公开了一种非易失性半导体存储器件，其包括存储单元单元，该存储单元包括形成在半导体衬底上的至少一个存储单元晶体管，并具有电荷累积层和控制栅极层的叠层结构，以及选择栅极晶体管 其源极/漏极扩散层区域连接到位线或源极线，并且其源极/漏极扩散层区域中的另一个连接到存储器单元单元。 选择栅极晶体管的源极扩散层区域的形状与选择栅极晶体管下面的漏极扩散层区域的形状不对称。

    Semiconductor memory device and manufacturing method thereof
    9.
    发明授权
    Semiconductor memory device and manufacturing method thereof 失效
    半导体存储器件及其制造方法

    公开(公告)号：US07629638B2

    公开(公告)日：2009-12-08

    申请号：US11319743

    申请日：2005-12-29

    申请人： Toshitake Yaegashi

    发明人： Toshitake Yaegashi

    IPC分类号： H01L29/788 ,  H01L21/336

    CPC分类号： H01L29/513 ,  H01L27/115 ,  H01L27/11568

    摘要： A semiconductor device, in which both a reduction in a resistivity of a gate electrode and stabilization of transistor characteristics is achieved, and a manufacturing method thereof are disclosed. According to one aspect of the present invention, it is provided a semiconductor device comprising a semiconductor substrate, a plurality of gate electrodes each including an electric charge storage layer formed on the semiconductor substrate through a first insulator, first and second conductor layers, and a second insulator disposed between the electric charge storage layer and the first conductor layer, a barrier insulator provided between the gate electrodes and being in contact with side surfaces alone of the gate electrodes, and an interlayer insulator provided in contact with an upper surface of the second conductor layer.

    摘要翻译： 公开了其中实现了栅电极的电阻率的降低和晶体管特性的稳定化的半导体器件及其制造方法。 根据本发明的一个方面，提供了一种半导体器件，包括半导体衬底，多个栅电极，每个栅电极包括通过第一绝缘体形成在半导体衬底上的电荷存储层，第一和第二导体层以及 设置在电荷存储层和第一导体层之间的第二绝缘体，设置在栅电极之间并与栅电极单独接触的隔离绝缘体，以及与第二导体层的上表面接触的层间绝缘体 导体层。

    Semiconductor memory device including multi-layer gate structure
    10.
    发明授权
    Semiconductor memory device including multi-layer gate structure 有权
    半导体存储器件包括多层门结构

    公开(公告)号：US07446364B2

    公开(公告)日：2008-11-04

    申请号：US11514705

    申请日：2006-08-30

    申请人： Toshitake Yaegashi

    发明人： Toshitake Yaegashi

    IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC分类号： H01L27/115 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L29/42324

    摘要： A semiconductor memory device includes a first select transistor, first stepped portion, and a first contact plug. The first select transistor is formed on a side of an upper surface of a substrate and has a first multi-layer gate. The first-stepped portion is formed by etching the substrate adjacent to the first multi-layer gate of the first select transistor such that the first stepped portion forms a cavity in the upper surface of the substrate. The first contact plug is formed in the first stepped portion.

    摘要翻译： 半导体存储器件包括第一选择晶体管，第一阶梯部分和第一接触插头。 第一选择晶体管形成在衬底的上表面的一侧，并且具有第一多层栅极。 通过蚀刻与第一选择晶体管的第一多层栅极相邻的衬底来形成第一阶梯部分，使得第一阶梯部分在衬底的上表面中形成空腔。 第一接触插塞形成在第一阶梯部分中。