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    Structure for optionally cascading shift registers
    1.
    发明授权
    Structure for optionally cascading shift registers 有权
    可选择级联移位寄存器的结构

    公开(公告)号：US6118298A

    公开(公告)日：2000-09-12

    申请号：US253313

    申请日：1999-02-18

    申请人： Trevor J. Bauer ,  Bruce A. Newgard ,  William E. Allaire ,  Steven P. Young

    发明人： Trevor J. Bauer ,  Bruce A. Newgard ,  William E. Allaire ,  Steven P. Young

    IPC分类号： H03K19/173 ,  H03K19/177

    CPC分类号： G11C19/00 ,  H03K19/1736 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17768

    摘要： A set of logic elements can be configured as a cascadable shift register. In one embodiment, a logic element for an FPGA can be configured as any one of a random access memory, a cascadable shift register and a lookup table. The data-in path to the shift register includes a cascade multiplexer for optionally forming large shift registers using multiple logic elements. Each logic element includes a plurality of memory cells which are interconnected such that the data output of each memory cell can serve as the input to the next memory cell, causing the logic element to function as a shift register. The cascade multiplexer allows the last bit of one logic element to be connected to the first bit of the next logic element, bypassing any decode logic of the lookup table. Variable tap shift registers of arbitrary length can be created by cascading lookup tables of plural logic elements in series. The lookup table decode logic plus additional multiplexers can be used to select any memory cell (not necessarily the last memory cell) of the shift register.

    摘要翻译： 一组逻辑元件可以配置为可级联移位寄存器。 在一个实施例中，用于FPGA的逻辑元件可以被配置为随机存取存储器，级联移位寄存器和查找表中的任何一个。 到移位寄存器的数据输入路径包括级联多路复用器，用于可选地使用多个逻辑元件形成大移位寄存器。 每个逻辑元件包括互连的多个存储器单元，使得每个存储器单元的数据输出可以用作到下一个存储单元的输入，使逻辑元件用作移位寄存器。 级联多路复用器允许一个逻辑元件的最后一位连接到下一个逻辑元件的第一位，绕过查找表的任何解码逻辑。 可以通过串联多个逻辑元件的查询表来创建任意长度的可变抽头移位寄存器。 查找表解码逻辑加上附加多路复用器可用于选择移位寄存器的任何存储单元（不一定是最后一个存储单元）。

    FIFO in FPGA having logic elements that include cascadable shift registers
    2.
    发明授权
    FIFO in FPGA having logic elements that include cascadable shift registers 有权
    FPGA中的FIFO具有包括可级联移位寄存器的逻辑元件

    公开(公告)号：US06262597B1

    公开(公告)日：2001-07-17

    申请号：US09624515

    申请日：2000-07-24

    申请人： Trevor J. Bauer ,  Bruce A. Newgard ,  William E. Allaire ,  Steven P. Young

    发明人： Trevor J. Bauer ,  Bruce A. Newgard ,  William E. Allaire ,  Steven P. Young

    IPC分类号： H03K19177

    CPC分类号： G11C19/00 ,  H03K19/1736 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17768

    摘要： A set of logic elements can be configured as a cascadable shift register. In one embodiment, a logic element for an FPGA can be configured as any one of a random access memory, a cascadable shift register and a lookup table. The data-in path to the shift register includes a cascade multiplexer for optionally forming large shift registers using multiple logic elements. Each logic element includes a plurality of memory cells which are interconnected such that the data output of each memory cell can serve as the input to the next memory cell, causing the logic element to function as a shift register. The cascade multiplexer allows the last bit of one logic element to be connected to the first bit of the next logic element, bypassing any decode logic of the lookup table. Variable tap shift registers of arbitrary length can be created by cascading lookup tables of plural logic elements in series. The lookup table decode logic plus additional multiplexers can be used to select any memory cell (not necessarily the last memory cell) of the shift register.

    摘要翻译： 一组逻辑元件可以配置为可级联移位寄存器。 在一个实施例中，用于FPGA的逻辑元件可以被配置为随机存取存储器，级联移位寄存器和查找表中的任何一个。 到移位寄存器的数据输入路径包括级联多路复用器，用于可选地使用多个逻辑元件形成大移位寄存器。 每个逻辑元件包括互连的多个存储器单元，使得每个存储器单元的数据输出可以用作到下一个存储器单元的输入，使逻辑元件用作移位寄存器。 级联多路复用器允许一个逻辑元件的最后一位连接到下一个逻辑元件的第一位，绕过查找表的任何解码逻辑。 可以通过串联多个逻辑元件的查询表来创建任意长度的可变抽头移位寄存器。 查找表解码逻辑加上附加多路复用器可用于选择移位寄存器的任何存储单元（不一定是最后一个存储单元）。

    Formation of columnar application specific circuitry using a columnar programmable device
    4.
    发明授权
    Formation of columnar application specific circuitry using a columnar programmable device 有权
    使用柱状可编程器件形成柱状应用专用电路

    公开(公告)号：US07965102B1

    公开(公告)日：2011-06-21

    申请号：US12248668

    申请日：2008-10-09

    申请人： Trevor J. Bauer ,  Steven P. Young

    发明人： Trevor J. Bauer ,  Steven P. Young

    IPC分类号： H01L25/00

    CPC分类号： G06F17/5054 ,  H03K19/177

    摘要： A columnar programmable device (PD) design converted to a columnar application specific integrated circuit-like (ASIC-like) design is described. A user design is instantiated in a PD having a columnar architecture associated with the columnar PD design. The columnar architecture has adjacent columns of circuitry, and one or more of the columns of circuitry as associated with instantiation of the user design in the PD are identified. At least a portion of one or more of the identified columns are swapped with application specific circuitry for implementing all or part of the user design for converting the columnar PD design to the columnar ASIC-like design.

    摘要翻译： 描述了转换为柱状专用集成电路（ASIC）设计的柱状可编程器件（PD）设计。 在具有与柱状PD设计相关联的柱状结构的PD中实例化用户设计。 柱状架构具有相邻的电路列，并且识别与PD中的用户设计的实例化相关联的一个或多个电路列。 一个或多个所标识的列的至少一部分与应用专用电路交换，用于实现用于将柱状PD设计转换成柱状ASIC样设计的全部或部分用户设计。

    Structures and methods to avoiding hold time violations in a programmable logic device
    5.
    发明授权
    Structures and methods to avoiding hold time violations in a programmable logic device 有权
    避免可编程逻辑器件中的保持时间违规的结构和方法

    公开(公告)号：US07548089B1

    公开(公告)日：2009-06-16

    申请号：US11880724

    申请日：2007-07-24

    申请人： Trevor J. Bauer ,  Ramakrishna K. Tanikella ,  Steven P. Young

    发明人： Trevor J. Bauer ,  Ramakrishna K. Tanikella ,  Steven P. Young

    IPC分类号： H01L25/00

    CPC分类号： H03K19/17736 ,  H03K19/00323

    摘要： Structures and methods of avoiding hold time violations in a design implemented in a PLD. In a programmable device, the delay of a signal path varies, e.g., depending on the separation between the source and destination of the signal. An optional delay element is provided between a programmable interconnect structure and a destination logic element having a clock skew relative to the source. The optional delay element is programmed by the implementation software to introduce a delay on the signal path when necessary to meet the hold time requirements for the destination logic element. The optional delay is designed to be large enough to overcome hold-time violations even for the largest possible clock skew and the smallest possible signal delay. When no hold time violation occurs, the optional delay element is configured to bypass the additional delay, to avoid imposing a large setup requirement on the signal.

    摘要翻译： 在PLD中实现的设计中避免持续时间违规的结构和方法。 在可编程设备中，信号路径的延迟例如取决于信号的源和目的地之间的间隔而变化。 在可编程互连结构和具有相对于源的时钟偏移的目的地逻辑元件之间提供可选的延迟元件。 可选延迟元件由实现软件编程，以在必要时在信号路径上引入延迟以满足目的地逻辑元件的保持时间要求。 可选延迟被设计为足够大，以克服即使对于最大可能的时钟偏移和尽可能小的信号延迟的保持时间违规。 当没有发生保持时间违规时，可选的延迟元件被配置为绕过附加延迟，以避免对信号施加大的设置要求。

    Multi-product die configurable as two or more programmable integrated circuits of different logic capacities
    6.
    发明授权
    Multi-product die configurable as two or more programmable integrated circuits of different logic capacities 有权
    多产品管芯可配置为具有不同逻辑容量的两个或多个可编程集成电路

    公开(公告)号：US07345507B1

    公开(公告)日：2008-03-18

    申请号：US11333991

    申请日：2006-01-17

    申请人： Steven P. Young ,  Trevor J. Bauer ,  F. Erich Goetting ,  P. Hugo Lamarche ,  Patrick J. McGuire ,  Kwansuhk Oh ,  Raymond C. Pang ,  Bruce E. Talley ,  Paul Ying-Fung Wu

    发明人： Steven P. Young ,  Trevor J. Bauer ,  F. Erich Goetting ,  P. Hugo Lamarche ,  Patrick J. McGuire ,  Kwansuhk Oh ,  Raymond C. Pang ,  Bruce E. Talley ,  Paul Ying-Fung Wu

    IPC分类号： H01L25/00

    CPC分类号： H03K19/177

    摘要： A multi-product integrated circuit die includes at least two different portions, of which at least one portion can be deliberately rendered non-operational in some manner (e.g., non-functional, inaccessible, and/or non-programmable) within the package. A selection code storage circuit stores a product selection code. A first value of the product selection code selects the option where both the first and second portions of the first die are operational. A second value of the product selection code selects the option where only the first portion of the first die is operational. The selection code storage circuit can include non-volatile memory or a fuse structure, or the product selection code can be configured as a package bonding option. The product selection code can also enable boundary scan for the operational portion of the die, and omit from the boundary scan chain any portions of the die that are deliberately rendered non-operational.

    摘要翻译： 多产品集成电路管芯包括至少两个不同的部分，其中至少一个部分可以以某种方式（例如，非功能的，不可访问的和/或不可编程的）被故意地变为不可操作的。 选择码存储电路存储产品选择码。 产品选择代码的第一个值选择第一模具的第一和第二部分都可操作的选项。 产品选择代码的第二个值选择仅第一个模具的第一部分可操作的选项。 选择代码存储电路可以包括非易失性存储器或熔丝结构，或者可以将产品选择代码配置为封装绑定选项。 产品选择代码还可以为模具的操作部分启用边界扫描，并且从边界扫描链中省略故意使其不可操作的模具的任何部分。

    Architecture and method for partially reconfiguring an FPGA
    7.
    发明授权
    Architecture and method for partially reconfiguring an FPGA 有权
    部分重新配置FPGA的架构和方法

    公开(公告)号：US06526557B1

    公开(公告)日：2003-02-25

    申请号：US09624818

    申请日：2000-07-25

    申请人： Steven P. Young ,  Trevor J. Bauer

    发明人： Steven P. Young ,  Trevor J. Bauer

    IPC分类号： G06F1750

    CPC分类号： H03K19/17756

    摘要： An FPGA architecture and method enables partial reconfiguration of selected configurable logic blocks (CLBs) connected to an address line without affecting other CLBs connected to the same address line. Partial reconfiguration at a memory cell resolution is achieved by manipulating the input voltages applied to the address and data lines of an FPGA so that certain memory cells are programmed while other memory cells are not programmed. In addition, partial reconfiguration at a CLB resolution can be achieved by hardwiring the FPGA to enable selection of individual CLBs for reconfiguration.

    摘要翻译： FPGA架构和方法使得能够部分重新配置连接到地址线的所选择的可配置逻辑块（CLB），而不会影响连接到同一地址线的其他CLB。 通过操纵施加到FPGA的地址和数据线的输入电压来实现存储器单元分辨率的部分重新配置，使得某些存储器单元被编程而其他存储器单元未被编程。 此外，CLB分辨率的部分重新配置可以通过硬连线FPGA来实现，以便能够选择单个CLB进行重新配置。

    FPGA lookup table with NOR gate write decoder and high speed read decoder
    8.
    发明授权
    FPGA lookup table with NOR gate write decoder and high speed read decoder 有权
    具有NOR门写解码器和高速读取解码器的FPGA查找表

    公开(公告)号：US06445209B1

    公开(公告)日：2002-09-03

    申请号：US09566398

    申请日：2000-05-05

    申请人： Steven P. Young ,  Trevor J. Bauer ,  Richard A. Carberry

    发明人： Steven P. Young ,  Trevor J. Bauer ,  Richard A. Carberry

    IPC分类号： H03K19177

    CPC分类号： H03K19/17728 ,  H03K19/1737

    摘要： A fast, space-efficient lookup table (LUT) for programmable logic devices (PLDs) in which the write decoder, read decoder and memory block of the LUT are modified to improve performance while providing a highly efficient layout. Both the write decoder and the read decoder are controlled by LUT input signals, and data signals are transmitted directly to each memory circuit of the memory block (i.e., without passing through the write decoder). The write decoder includes NOR gates that generate select signals used to address individual memory circuits during write operations. For dynamic latching during reading or shifting, each memory circuit includes an inverter circuit connected between the memory cell and the output terminal of the memory circuit. The read decoder includes a multiplexing circuit made up of a series of 2-to-1 multiplexers that are directly controlled by the input signals received from the interconnect resources of the PLD. In one embodiment, a configurable logic block is provided with a single write decoder that is shared by a first LUT and a second LUT.

    摘要翻译： 用于可编程逻辑器件（PLD）的快速，节省空间的查找表（LUT），其中修改LUT的写解码器，读取解码器和存储器块以提供高性能，同时提供高效布局。 写解码器和读取解码器都由LUT输入信号控制，数据信号被直接发送到存储器块的每个存储电路（即不经过写入解码器）。 写入解码器包括NOR门，其产生用于在写入操作期间寻址各个存储器电路的选择信号。 对于读取或移位期间的动态锁存，每个存储器电路包括连接在存储器单元和存储器电路的输出端之间的反相器电路。 读取解码器包括由从PLD的互连资源接收的输入信号直接控制的一系列2对1复用器组成的复用电路。 在一个实施例中，可配置逻辑块被提供有由第一LUT和第二LUT共享的单个写入解码器。

    Configurable logic element with ability to evaluate five and six input functions
    9.
    发明授权
    Configurable logic element with ability to evaluate five and six input functions 失效
    可配置逻辑元件，具有评估五个和六个输入功能的能力

    公开(公告)号：US5920202A

    公开(公告)日：1999-07-06

    申请号：US835088

    申请日：1997-04-04

    申请人： Steven P. Young ,  Shekhar Bapat ,  Kamal Chaudhary ,  Trevor J. Bauer ,  Roman Iwanczuk

    发明人： Steven P. Young ,  Shekhar Bapat ,  Kamal Chaudhary ,  Trevor J. Bauer ,  Roman Iwanczuk

    IPC分类号： H01L25/00 ,  H03K19/173 ,  H03K19/177 ,  G06F7/38

    CPC分类号： H03K19/17728 ,  H03K19/1737 ,  H03K19/17704

    摘要： The invention provides a Configurable Logic Element (CLE) preferably included in each of an array of identical tiles. A CLE according to the invention has four function generators. The outputs of two function generators are combined with a fifth independent input in a five-input-function multiplexer or function generator to produce an output that can be any function of five inputs, or some functions of up to nine inputs. The outputs of the other two function generators are similarly combined. The outputs of the two five-input-function multiplexers or function generators are then combined with a sixth independent input in a first six-input-function multiplexer or function generator, and with a different sixth independent input in a second six-input-function multiplexer or function generator. The two six-input-function multiplexers or function generators therefore produce two outputs of which one can be any function of six inputs; the other output can be any function of six inputs provided that five inputs are shared between the two 6-input functions. Some functions of up to nineteen inputs can also be generated in a single CLE.

    摘要翻译： 本发明提供了优选地包括在相同瓦片的阵列中的每一个中的可配置逻辑元件（CLE）。 根据本发明的CLE具有四个功能发生器。 两个功能发生器的输出与五输入功能多路复用器或函数发生器中的第五个独立输入组合，以产生可以是五个输入或多达九个输入的一些功能的输出。 其他两个功能发生器的输出类似地组合。 然后，两个五输入功能多路复用器或函数发生器的输出与第六个六输入函数多路复用器或函数发生器中的第六个独立输入组合，并在第六个六输入函数中与不同的第六独立输入进行组合 多路复用器或函数发生器。 因此，两个六输入功能多路复用器或函数发生器产生两个输出，其中一个可以是六个输入的任何功能; 另外的输出可以是六个输入的任何功能，只要在两个6输入功能之间共享五个输入。 也可以在单个CLE中生成多达十九个输入的某些功能。

    FPGA repeatable interconnect structure with hierarchical interconnect lines
    10.
    发明授权
    FPGA repeatable interconnect structure with hierarchical interconnect lines 失效
    具有分层互连线路的FPGA可重复互连结构

    公开(公告)号：US5914616A

    公开(公告)日：1999-06-22

    申请号：US806997

    申请日：1997-02-26

    申请人： Steven P. Young ,  Kamal Chaudhary ,  Trevor J. Bauer

    发明人： Steven P. Young ,  Kamal Chaudhary ,  Trevor J. Bauer

    IPC分类号： H01L25/00 ,  H03K19/173 ,  H03K19/177

    CPC分类号： H03K19/17796 ,  H03K19/1737 ,  H03K19/17704

    摘要： The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. A combination of single-length lines connecting to adjacent tiles and intermediate-length lines connecting to tiles several tiles away creates an interconnect hierarchy which allows any logic block to be connected to any other logic block, yet also allows for fast paths to both adjacent tiles and tiles some distance away. Longer interconnect lines may be included as a third level of hierarchy to permit interconnection of widely separated tiles. In a preferred embodiment, from a given tile an intermediate-length line connects to the tile three tiles away, then continues and connects to the tile six tiles away. In this embodiment, the intermediate-length line does not connect to the intervening tiles one, two, four, and five tiles away.

    摘要翻译： 本发明提供了优选地包括在相同瓦片阵列中的FPGA互连结构。 连接到相邻瓦片的单条线和连接到瓦片几个瓦片的中间线的组合创建互连层级，其允许任何逻辑块连接到任何其他逻辑块，但是也允许到相邻瓦片的快速路径 和瓷砖有一段距离。 可以将更长的互连线包括为第三层次以允许广泛分隔的瓷砖的互连。 在优选实施例中，从给定的瓦片中，中间线连接到瓦片三瓦片，然后继续并连接到瓦片六瓦片。 在该实施例中，中间长度线不连接到中间瓦片一个，两个，四个和五个瓦片。