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公开(公告)号：US06034914A
公开(公告)日：2000-03-07
申请号：US179893
申请日：1998-10-28
CPC分类号： G11C29/80
摘要： There is provided a semiconductor memory device which comprises a plurality of memory cells, a plurality of bit lines connected with the plurality of memory cells, a plurality of word lines connected with the plurality of memory cells, a plurality of data line pairs, a plurality of transfer gates for effecting controlled connection of the plurality of bit lines with the plurality of data lines, a plurality of column select lines for controlling conductibility of the plurality of the transfer gates, and a column select line drive circuit for simultaneously selecting and driving at least two of the plurality of column select lines corresponding to one-time column address input from the outside of the chip.
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公开(公告)号：US06404698B1
公开(公告)日：2002-06-11
申请号：US09496032
申请日：2000-01-21
IPC分类号： G11C800
CPC分类号： G11C29/80
摘要： There is provided a semiconductor memory device which comprises a plurality of memory cells, a plurality of bit lines connected with the plurality of memory cells, a plurality of word lines connected with the plurality of memory cells, a plurality of data line pairs, a plurality of transfer gates for effecting controlled connection of the plurality of bit lines with the plurality of data lines, a plurality of column select lines for controlling conductibility of the plurality of the transfer gates, and a column select line drive circuit for simultaneously selecting and driving at least two of the plurality of column select lines corresponding to one-time column address input from the outside of the chip.
摘要翻译： 提供了一种半导体存储器件，其包括多个存储器单元，与多个存储单元连接的多个位线，与多个存储单元连接的多个字线，多个数据线对，多个 用于实现多个位线与多条数据线的受控连接的多个传输门，用于控制多个传送门的导电性的多个列选择线，以及用于同时选择和驱动的列选择线驱动电路 对应于从芯片外部输入的一次列地址的多个列选择线中的至少两个。
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公开(公告)号：US6097660A
公开(公告)日：2000-08-01
申请号：US53511
申请日：1998-04-02
IPC分类号： G11C11/401 , G11C5/02 , G11C8/12 , G11C11/407 , G11C11/409 , G11C11/4097 , H01L21/8242 , H01L27/108 , G11C8/00
CPC分类号： G11C5/025 , G11C11/4097 , G11C8/12
摘要： A semiconductor memory device comprises a plurality of memory banks each having a plurality of memory cell arrays and a plurality of sense amplifiers such that the memory cell arrays and the sense amplifiers are alternately disposed in a first direction, the memory banks being disposed in a second direction perpendicular to the first direction, a plurality of row decoders respectively provided in the first direction for the plurality of memory banks, a column decoder provided in the second direction with respect to the plurality of memory banks, a plurality of first data lines respectively provided in the second direction for the plurality of memory banks, and connected with the plurality of sense amplifiers in accordance with a signal outputted from the column decoder, a plurality of second data lines provided in the second direction, penetrating through the plurality of memory banks, and shared by the plurality of first data lines disposed for the plurality of memory banks, and a plurality of switching elements each having a first end connected to one of the plurality of first data lines and a second end connected to one of the plurality of second data lines, and controlled by a bank activation signal of a memory bank corresponding to the first data line connected to the first ends.
摘要翻译： 半导体存储器件包括多个存储器组，每个存储器组具有多个存储单元阵列和多个读出放大器，使得存储单元阵列和读出放大器交替地沿第一方向设置，存储体设置在第二 分别设置在多个存储体的第一方向的多个行解码器，相对于多个存储体设置在第二方向上的列解码器，分别设置有多个第一数据线 在所述多个存储体的第二方向上，并且根据从所述列解码器输出的信号与所述多个读出放大器连接;沿着所述第二方向设置的穿过所述多个存储体的多个第二数据线， 并且由为多个存储体设置的多个第一数据线和plu共享 开关元件的强度各自具有连接到多个第一数据线之一的第一端和连接到所述多条第二数据线之一的第二端，并且由对应于第一数据的存储体的存储体激活信号控制 线连接到第一端。
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公开(公告)号：US6094390A
公开(公告)日：2000-07-25
申请号：US72724
申请日：1998-05-06
IPC分类号： G11C11/401 , G11C7/10 , G11C7/12 , G11C7/18 , H01L21/8242 , H01L27/108 , G11C7/00
CPC分类号： H01L27/10897 , G11C7/1048 , G11C7/12 , G11C7/18
摘要： A semiconductor memory device with a semiconductor substrate and a plurality of element regions formed in the semiconductor is shown. The semiconductor memory device further includes at least one column gate and at least one equalizer in which they are formed as a set in at least one of the element regions.
摘要翻译： 示出了半导体衬底和半导体中形成的多个元件区的半导体存储器件。 半导体存储器件还包括至少一个列栅极和至少一个均衡器，其中它们在至少一个元件区域中形成为一组。
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公开(公告)号：US6002636A
公开(公告)日：1999-12-14
申请号：US199463
申请日：1998-11-25
IPC分类号： G11C11/41 , G11C5/02 , G11C8/08 , G11C11/401 , G11C11/407 , G11C11/408 , H01L21/8242 , H01L27/108 , G11C8/00
CPC分类号： G11C5/025 , G11C11/4085 , G11C8/08
摘要： This invention discloses the layout of word line driving circuits for driving word lines. A semiconductor memory device includes a memory cell array having a bit line, n memory cells connected to the bit line, and n word lines respectively connected to the n memory cells. The semiconductor memory device further includes n/2 first word line driving circuits for driving n/2 word lines of the n word lines, and n/2 second word line driving circuits for driving the remaining n/2 word lines of the n word lines. The second word line driving circuits are arranged at the positions where the second word line driving circuits face the first word line driving circuits via the memory cell array.
摘要翻译： 本发明公开了用于驱动字线的字线驱动电路的布局。 一种半导体存储器件包括具有位线的存储单元阵列，+ E，连接到位线的uns n + EE存储器单元，以及分别连接到+ E，uns n + EE的+ E，uns n + EE字线 记忆细胞 半导体存储器件还包括用于驱动+ E，n n + EE字线的n / 2个字线的n / 2个第一字线驱动电路和用于驱动剩余n / 2个字的n / 2个第二字线驱动电路 行+ E，uns n + EE字线。 第二字线驱动电路被布置在第二字线驱动电路经由存储单元阵列面对第一字线驱动电路的位置。
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公开(公告)号：US5703817A
公开(公告)日：1997-12-30
申请号：US748779
申请日：1996-11-14
IPC分类号： H01L21/82 , G11C11/401 , G11C17/00 , G11C29/00 , G11C29/04 , G11C29/44 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C7/00
CPC分类号： G11C29/785 , G11C29/44 , G11C29/804 , G11C29/808
摘要： A plurality of memory cells are arranged at crosspoints between a plurality of word lines and a plurality of bit lines. The memory cells include not only normal cells but also spare cells for saving defects. The saving of the defect is effected by replacing the word line or bit line connected to the normal cell with the word line or bit line connected to the spare cell. The replacement is effected by a corresponding pair of fuse circuit and deciding circuit, that is, the fuse circuit for storing the address of a word line or bit line to be replaced and the deciding circuit for, based on the address, deciding whether or not an accessed word line or bit line be replaced. As such a pair use is made of a plurality of pairs and a plurality of kinds are provided as the word lines or bit lines for replacement and can be used in accordance with the size of defects. It is, therefore, possible to effectively save the defective word line or bit line, while avoiding any uneffective replacement.
摘要翻译： 多个存储单元被布置在多个字线和多个位线之间的交叉点处。 存储单元不仅包括正常单元格，还包括用于保存缺陷的备用单元。 通过用连接到备用单元的字线或位线替换连接到正常单元的字线或位线来实现缺陷的保存。 该替换由对应的熔丝电路和判定电路对，即用于存储要替换的字线或位线的地址的熔丝电路和基于该地址的判定电路来决定是否 访问的字线或位线被替换。 这样一对使用由多对构成，并且提供多种类型作为用于替换的字线或位线，并且可以根据缺陷的尺寸使用。 因此，可以有效地保存有缺陷的字线或位线，同时避免任何不必要的更换。
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7.发明授权Semiconductor memory device having improved word line arrangement in a memory cell array 失效半导体存储器件具有改进的存储单元阵列中的字线布置
公开(公告)号：US5903022A
公开(公告)日：1999-05-11
申请号：US630461
申请日：1996-04-10
IPC分类号： G11C11/407 , G11C8/10 , G11C8/14 , G11C11/401 , H01L21/8242 , H01L27/108
摘要： A semiconductor memory device according to the present invention comprises a plurality of word lines constituted by gate wirings, a memory cell array having memory cells selectively arranged at nodes between the plurality of word lines and a plurality of bit lines, the memory cell array having a plurality of subarrays which are divided in a word line arrangement direction, a main row decoder arranged at least one end of the memory cell array in the word line arrangement direction, a plurality of sub-row decoders arranged at least one end of each of the plurality of subarrays, and a first wiring layer formed on a layer above the gate wirings and extending from the sub-row decoder, and the first wiring layer is wired to a position where the subarray is divided by two in the word line arrangement direction to be brought into contact with the gate wiring.
摘要翻译： 根据本发明的半导体存储器件包括由栅极布线构成的多个字线，存储单元阵列，其具有选择性地布置在多个字线之间的节点处的存储单元和多个位线，所述存储单元阵列具有 以字线排列方向划分的多个子阵列，排列在字线排列方向上的存储单元阵列的至少一端的主行解码器，多个子行解码器， 多个子阵列，以及形成在栅极布线上方并从子行解码器延伸的层上的第一布线层，并且第一布线层布线到字线在字线排列方向上被二分割的位置， 与门线接触。
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公开(公告)号：US06288927B1
公开(公告)日：2001-09-11
申请号：US09587263
申请日：2000-06-05
IPC分类号： G11C506
CPC分类号： H01L27/10897 , G11C7/1048 , G11C7/12 , G11C7/18
摘要： A semiconductor memory device includes a semiconductor substrate and a plurality of element regions formed in the semiconductor, wherein at least one column gate and at least one equalizer are formed as a set in one element region of the plurality of element regions. In one embodiment, a set of a column gate and an equalizer share a diffusion layer with an adjacent set of a column gate and an equalizer. In a second embodiment, a gate electrode of the equalizer is disposed to divide a diffusion layer into six regions. In other embodiments, the equalizer is surrounded by at least a gate electrode of a column gate. In yet other embodiments, the sets of column gates and equalizers are disposed parallel to a bit line.
摘要翻译： 半导体存储器件包括半导体衬底和形成在半导体中的多个元件区域，其中至少一个列栅极和至少一个均衡器作为一组在多个元件区域的一个元件区域中形成。 在一个实施例中，一列列门和均衡器与一个相邻的一列列门和一均衡器共享扩散层。 在第二实施例中，设置均衡器的栅电极以将扩散层分成六个区域。 在其他实施例中，均衡器由至少栅极的栅电极包围。 在其他实施例中，列门和均衡器的集合平行于位线布置。
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9.发明授权Semiconductor memory device having folded bit line array and an open bit line array with imbalance correction 失效具有折叠位线阵列的半导体存储器件和具有不平衡校正的开放位线阵列
公开(公告)号：US5761109A
公开(公告)日：1998-06-02
申请号：US614537
申请日：1996-03-13
IPC分类号： G11C11/409 , G11C11/4097 , H01L21/8242 , H01L27/108 , G11C5/06
CPC分类号： G11C11/4097
摘要： A dynamic semiconductor memory device according to the present invention comprises at least first and second memory cell arrays having a plurality of memory cells selectively arranged at respective intersections of a plurality of word lines and a plurality of bit lines, a first sense amplifier section connected at an end of the first cell array to a plurality of bit line pairs formed by part of the plurality of bit lines of the first cell array, the plurality of bit line pairs having a folded bit line configuration, a second sense amplifier section connected to sets of bit line pairs, each formed by one of the remaining bit lines of the first cell array and one of part of the plurality of bit lines of the second cell array, the plurality of bit line pairs having an open bit line configuration, and a correction circuit for correcting the level of ease for reading data "0" and that of reading data "1".
摘要翻译： 根据本发明的动态半导体存储器件包括至少第一和第二存储器单元阵列，其具有选择性地布置在多个字线和多个位线的各个交点处的多个存储器单元，第一读出放大器部分连接在 第一单元阵列的一端到由第一单元阵列的多个位线的一部分形成的多个位线对，多个位线对具有折叠位线配置，第二读出放大器部分连接到组 的位线对，每个位线对由第一单元阵列的剩余位线之一和第二单元阵列的多个位线的一部分之一形成，多个位线对具有打开的位线配置，以及 用于校正读取数据“0”的容易程度的校正电路和读取数据“1”的校正电路。
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10.发明授权公开(公告)号：US08120948B2
公开(公告)日：2012-02-21
申请号：US12561495
申请日：2009-09-17
申请人： Masahiko Nakayama , Hisanori Aikawa , Tsuneo Inaba , Kenji Tsuchida , Sumio Ikegawa , Hiroaki Yoda , Naoharu Shimomura
发明人： Masahiko Nakayama , Hisanori Aikawa , Tsuneo Inaba , Kenji Tsuchida , Sumio Ikegawa , Hiroaki Yoda , Naoharu Shimomura
IPC分类号： G11C11/00
CPC分类号： H01L27/228 , G11C11/161 , G11C11/1675
摘要： A data writing method for a magnetoresistive effect element of an aspect of the present invention including generating a write current in which a falling period from the start of a falling edge to the end of the falling edge is longer than a rising period from the start of a rising edge to the end of the rising edge, and flowing the write current through the magnetoresistive effect element which comprises a first magnetic layer having an invariable magnetizing direction, a second magnetic layer having a variable magnetizing direction, and a tunnel barrier layer provided between the first magnetic layer and the second magnetic layer, to change the magnetizing direction of the second magnetic layer.
摘要翻译： 一种用于本发明一个方面的磁阻效应元件的数据写入方法，包括产生写入电流，其中从下降沿开始到下降沿结束的下降周期长于从开始 上升沿到上升沿结束，并且使写入电流流过磁阻效应元件，该磁阻效应元件包括具有不变磁化方向的第一磁性层，具有可变磁化方向的第二磁性层和设置在可变磁化方向之间的隧道势垒层， 第一磁性层和第二磁性层，以改变第二磁性层的磁化方向。
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