公开(公告)号：US10553715B2

公开(公告)日：2020-02-04

申请号：US15917168

申请日：2018-03-09

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Nozomu Harada

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/461 ,  H01L21/475 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/786 ,  H01L29/417 ,  H01L29/10 ,  H01L29/775 ,  H01L29/06

摘要： An SGT is formed that includes Si pillars. The SGT includes WSi2 layers serving as wiring alloy layers and constituted by first alloy regions that are connected to the entire peripheries of impurity regions serving as sources or drains located in lower portions of the Si pillars, are formed in a self-aligned manner with the impurity regions in a tubular shape, and contain the same impurity atom as the impurity regions and a second alloy region that is partly connected to the peripheries of the first alloy regions and contains the same impurity atom as the impurity regions.

公开(公告)号：US10535756B2

公开(公告)日：2020-01-14

申请号：US16241332

申请日：2019-01-07

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Nozomu Harada

IPC分类号： H01L21/8238 ,  H01L29/66 ,  H01L29/423 ,  H01L21/225 ,  H01L21/308 ,  H01L29/40

摘要： The method for producing a pillar-shaped semiconductor device includes a step of providing a structure that includes, on an i layer substrate, a Si pillar and an impurity region located in a lower portion of the Si pillar and serving as a source or a drain, a step of forming a SiO2 layer that extends in a horizontal direction and is connected to an entire periphery of the impurity region in plan view, a step of forming a SiO2 layer on the SiO2 layer such that the SiO2 layer surrounds the Si pillar in plan view, a step of forming a resist layer that is partly connected to the SiO2 layer in plan view, and a step of forming a SiO2 layer by etching the SiO2 layer below the SiO2 layer and the resist layer using the SiO2 layer and the resist layer as masks.

公开(公告)号：US09673321B2

公开(公告)日：2017-06-06

申请号：US14806053

申请日：2015-07-22

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Nozomu Harada

IPC分类号： H01L29/78 ,  H01L21/225 ,  H01L21/24 ,  H01L21/265 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L21/285

CPC分类号： H01L29/66666 ,  H01L21/225 ,  H01L21/24 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/28531 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/768 ,  H01L21/76805 ,  H01L21/823437 ,  H01L21/823487 ,  H01L21/823885 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/41741 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/7827

摘要： An opening extending through a gate insulating layer and a gate conductor layer is formed in the circumferential portion of a Si pillar at an intermediate height of the Si pillar. A laminated structure including two sets each including a Ni film, a poly-Si layer containing donor or acceptor impurity atoms, and a SiO2 layer is formed so as to surround the opening. A heat treatment is carried out to form silicide from the poly-Si layers and this silicide formation causes the resultant NiSi layers to protrude and come into contact with the side surface of the Si pillar. The donor or acceptor impurity atoms diffuse from the NiSi layers into the Si pillar to thereby form an N+ region and a P+ region serving as a source or a drain of SGTs.

公开(公告)号：US20160204251A1

公开(公告)日：2016-07-14

申请号：US14976691

申请日：2015-12-21

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Nozomu Harada

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/423 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/417

CPC分类号： H01L29/41741 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/8221 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823885 ,  H01L27/0688 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/42356 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7848

摘要： A SiO2 layer is formed at a middle of a Si pillar. An opening is formed in a gate insulating layer and a gate conductor layer in a peripheral portion that includes a side surface of the SiO2 layer. Two stacks of layers, each stack being constituted by a Ni layer, a poly-Si layer containing a donor or acceptor impurity atom, and a SiO2 layer, are formed in a peripheral portion of the opening, and heat treatment is performed to silicidate the poly-Si layers into NiSi layers. The NiSi layers protrude and come into contact with the side surface of the Si pillar by silicidation, and a donor or acceptor impurity atom diffuses from the NiSi layers into the Si pillar. Thus an N+ region and a P+ region serving as a source and a drain of surrounding gate MOS transistors are respectively formed above and under the SiO2 layer.

摘要翻译： 在Si柱的中间形成SiO 2层。 在包括SiO 2层的侧面的周边部分的栅极绝缘层和栅极导体层中形成有开口。 在开口的周边部形成有两层叠层，每层由Ni层构成，含有供体或受主杂质原子的多晶硅层和SiO 2层，进行热处理，使硅酸盐化 多晶硅层成NiSi层。 NiSi层通过硅化物突出并与Si柱的侧表面接触，并且施主或受主杂质原子从NiSi层扩散到Si柱中。 因此，分别在SiO 2层的上方和下方形成用作围绕栅极MOS晶体管的源极和漏极的N +区域和P +区域。

公开(公告)号：US11380780B2

公开(公告)日：2022-07-05

申请号：US16992352

申请日：2020-08-13

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Nozomu Harada ,  Yoshiaki Kikuchi

IPC分类号： H01L29/66 ,  H01L21/225 ,  H01L21/308 ,  H01L21/02 ,  H01L21/306 ,  H01L29/423 ,  H01L29/786

摘要： A SiO2 layer 5 is formed in the bottom portion of a Si pillar 3 and on an i-layer substrate 2. Subsequently, a gate HfO2 layer 11b is formed so as to surround the side surface of the Si pillar 3, and a gate TiN layer 12b is formed so as to surround the HfO2 layer 11b. Subsequently, P+ layers 18 and 32 containing an acceptor impurity at a high concentration and serving as a source and a drain are simultaneously or separately formed by a selective epitaxial crystal growth method on the exposed side surface of the bottom portion of and on the top portion of the Si pillar 3. Thus, an SGT is formed on the i-layer substrate 2.

公开(公告)号：US10734391B2

公开(公告)日：2020-08-04

申请号：US16238816

申请日：2019-01-03

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Nozomu Harada

IPC分类号： H01L21/225 ,  H01L27/11 ,  H01L23/485 ,  H01L29/423 ,  H01L21/768 ,  H01L23/522 ,  H01L29/66 ,  H01L29/78 ,  H01L21/20 ,  H01L21/28 ,  H01L21/285 ,  H01L21/76 ,  H01L21/764 ,  H01L21/822 ,  H01L21/8234 ,  H01L23/528 ,  H01L29/04 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417 ,  H01L29/49 ,  H01L21/308 ,  H01L21/8238 ,  H01L29/16 ,  H01L29/51 ,  H01L21/311 ,  H01L23/532

摘要： A first contact hole is formed so as to extend to a NiSi layer as a lower wiring conductor layer connecting to an N+ layer of an SGT formed within a Si pillar, and so as to extend through a NiSi layer as an upper wiring conductor layer connecting to a gate TiN layer, and a NiSi layer as an intermediate wiring conductor layer connecting to an N+ layer. A second contact hole is formed so as to extend to the NiSi layer, and surround, in plan view, the first contact hole. An insulating SiO2 layer is formed on a side surface of the NiSi layer. A wiring metal layer in the contact holes connects the NiSi layer and the NiSi layer to each other.

公开(公告)号：US10658371B2

公开(公告)日：2020-05-19

申请号：US16225146

申请日：2018-12-19

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Nozomu Harada

IPC分类号： H01L21/225 ,  H01L27/11 ,  H01L29/786 ,  H01L21/324 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66

摘要： A method for producing a pillar-shaped semiconductor device includes, forming a first semiconductor pillar, a second semiconductor pillar, and a third semiconductor pillar on a substrate. A gate insulating layer and gate conductor layer are formed surrounding each of the pillars and impurity regions are formed in each pillar. The gate conductor layer is selectively processed to form gate conductors around the pillars and to interconnect the gate conductors.

公开(公告)号：US10651189B2

公开(公告)日：2020-05-12

申请号：US16148099

申请日：2018-10-01

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Nozomu Harada

IPC分类号： H01L27/1157 ,  H01L29/792 ,  H01L27/11582 ,  H01L27/11565 ,  H01L21/28 ,  H01L27/11575 ,  H01L27/11573

摘要： A method for producing a pillar-shaped semiconductor memory device includes forming a mask on a semiconductor substrate and etching to form a semiconductor pillar on the semiconductor substrate. A tunnel insulating layer is formed and a data charge storage insulating layer is formed so as to surround the tunnel insulating layer, and a first conductor layer and a second interlayer insulating layer are formed on the semiconductor pillar. A stacked material layer is formed in a direction perpendicular to an upper surface of the semiconductor substrate, the stacked material layer including the first conductor layer and the second interlayer insulating layer. Data writing and erasing due to charge transfer between the semiconductor pillar and the data charge storage insulating layer through the tunnel insulating layer is performed by application of a voltage to the first conductor layer.

公开(公告)号：US10593682B2

公开(公告)日：2020-03-17

申请号：US16296564

申请日：2019-03-08

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Nozomu Harada

IPC分类号： H01L21/285 ,  H01L27/11 ,  H01L29/423 ,  H01L29/786 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L29/78 ,  H01L29/45 ,  H01L29/49

摘要： A method for producing a semiconductor memory device includes forming two Si pillars on a substrate. In the Si pillars, inverter circuits are formed. The inverter circuits include drive N-channel SGTs each including first and second N+ layers functioning as a source and a drain, and load SGTs each including first and second P+ layers functioning as a source and drain. Selection SGTs each including third and fourth N+ layers functioning as a source and a drain are formed above SiO2 layers disposed above the inverter circuits. The first N+ layer is connected to a ground wiring metal layer. The first P+ layers are connected to a power supply wiring metal layer through a NiSi layer. Gate TiN layers are connected to a word-line wiring metal layer through a NiSi layer. The third N+ layers are connected to an inverted bit-line wiring metal layer and a bit-line wiring metal layer.

公开(公告)号：US10483376B1

公开(公告)日：2019-11-19

申请号：US16520892

申请日：2019-07-24

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Hiroki Nakamura ,  Nozomu Harada

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/3213 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/28 ,  H01L29/06

摘要： A method for producing a semiconductor device includes depositing a first insulating film and a second insulating film on a planar semiconductor layer formed on a substrate; forming a first hole for forming a gate electrode in the second insulating film; filling the first hole with a first metal to form the gate electrode; forming a side wall formed of a third insulating film on an upper surface of the gate electrode and a side surface of the first hole; performing etching through, as a mask, the side wall formed of the third insulating film, to form a second hole in the gate electrode and the first insulating film; forming a gate insulating film on a side surface of the second hole; and epitaxially growing a semiconductor layer, within the second hole, on the planar semiconductor layer to form a first pillar-shaped semiconductor layer.