公开(公告)号：US20180323227A1

公开(公告)日：2018-11-08

申请号：US15586102

申请日：2017-05-03

Applicant: United Microelectronics Corp.

Inventor： Sheng Zhang ,  Wen-Bo Ding ,  Zhi-Rui Sheng ,  Chien-En Hsu ,  Chien-Kee Pang

IPC: H01L27/146 ,  H01L21/306 ,  H01L23/00

Abstract: A wafer level packaging method includes the following steps. A first wafer is bonded over a second wafer. A first grinding process on the first wafer is performed, to remove an upper chamfered edge of the first wafer and reduce a thickness of the first wafer. A trimming process is performed on the first wafer, to remove a lower chamfered edge of the first wafer to form a trimmed first wafer. A second grinding process is performed on the trimmed first wafer, to reduce a thickness of the trimmed first wafer.

公开(公告)号：US20160204158A1

公开(公告)日：2016-07-14

申请号：US14595167

申请日：2015-01-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-En Hsu ,  Chen Jie Gu

IPC: H01L27/146

CPC classification number: H01L27/14643 ,  H01L27/14612 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/14689

Abstract: The present invention relates to a CMOS image sensor device and a method of forming the same. The CMOS image sensor device includes a substrate, a deep trench isolation (DTI), a photodiode, an electrode and an interface region. The DTI and the photodiode are both disposed in the substrate. The electrode is disposed on the DTI. The interface region is formed adjacent to the DTI.

Abstract translation: 本发明涉及CMOS图像传感器装置及其形成方法。 CMOS图像传感器装置包括衬底，深沟槽隔离（DTI），光电二极管，电极和界面区域。 DTI和光电二极管均设置在基板中。 电极设在DTI上。 界面区域与DTI相邻形成。

公开(公告)号：US10580823B2

公开(公告)日：2020-03-03

申请号：US15586102

申请日：2017-05-03

Applicant: United Microelectronics Corp.

Inventor： Sheng Zhang ,  Wen-Bo Ding ,  Zhi-Rui Sheng ,  Chien-En Hsu ,  Chien-Kee Pang

IPC: H01L27/146 ,  H01L23/00

Abstract: A wafer level packaging method includes the following steps. A first wafer is bonded over a second wafer. A first grinding process on the first wafer is performed, to remove an upper chamfered edge of the first wafer and reduce a thickness of the first wafer. A trimming process is performed on the first wafer, to remove a lower chamfered edge of the first wafer to form a trimmed first wafer. A second grinding process is performed on the trimmed first wafer, to reduce a thickness of the trimmed first wafer.

公开(公告)号：US20190181119A1

公开(公告)日：2019-06-13

申请号：US15834519

申请日：2017-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Guo-Zhong Xing ,  Chien-En Hsu

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L25/00

Abstract: A stacked semiconductor device is provided, including a first semiconductor structure, a second semiconductor structure and a bonding structure disposed between the first and second semiconductor structures. The first semiconductor structure and the second semiconductor structure include first conductive pillars and second conductive pillars, respectively. The first semiconductor structure is stacked above the second semiconductor structure. The bonding structure contacts the first conductive pillars and the second conductive pillars, wherein the bonding structure comprises conductive paths for electrically connecting the first conductive pillars and the second conductive pillars.

公开(公告)号：US10804418B2

公开(公告)日：2020-10-13

申请号：US16283895

申请日：2019-02-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Guo-Zhong Xing ,  Cheng-Yu Hsieh ,  Chien-En Hsu

IPC: H01L31/0352 ,  H01L31/028 ,  H01L31/18 ,  H01L31/0216 ,  H01L31/103

Abstract: A photodetector includes a substrate, at least one nanowire and a cladding layer. The at least one nanowire is disposed on the substrate and has a semiconductor core. The cladding layer is disposed on sidewalls of the semiconductor core and includes an epitaxial semiconductor film in contact with the sidewalls of the semiconductor core, a metal film disposed on the outside of the epitaxial semiconductor film and a high-k material layer disposed on the outside of metal film.

公开(公告)号：US20160268230A1

公开(公告)日：2016-09-15

申请号：US14656704

申请日：2015-03-12

Applicant: United Microelectronics Corp.

Inventor： Sin-Shien Lin ,  Fei Wang ,  Chien-En Hsu

IPC: H01L25/065 ,  H01L23/532 ,  H01L23/48 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/53295 ,  H01L21/76898 ,  H01L23/291 ,  H01L23/3192 ,  H01L23/5226 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/08121 ,  H01L2224/08147 ,  H01L2224/08148 ,  H01L2224/80097 ,  H01L2224/80194 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/00014 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

Abstract: A stacked semiconductor structure includes a first wafer, a second wafer, a first insulting layer, and a second insulating layer. The first wafer includes a first front surface, a first back surface, and a first interconnection structure. The first interconnection structure includes at least a first top metal layer exposed on the first front surface of the first wafer. The second wafer includes a second front surface, a second back surface, and a second interconnection structure. The second interconnection structure includes at least a second top metal layer exposed on the second front surface of the second wafer. The first insulating layer is formed on the first front surface of the first wafer, and the second insulating layer is formed on the second front surface of the second wafer. The first insulating layer and the second insulating layer contact each other.

Abstract translation: 叠层半导体结构包括第一晶片，第二晶片，第一绝缘层和第二绝缘层。 第一晶片包括第一前表面，第一后表面和第一互连结构。 第一互连结构包括暴露在第一晶片的第一前表面上的至少第一顶金属层。 第二晶片包括第二前表面，第二后表面和第二互连结构。 第二互连结构包括暴露在第二晶片的第二前表面上的至少第二顶金属层。 第一绝缘层形成在第一晶片的第一前表面上，第二绝缘层形成在第二晶片的第二前表面上。 第一绝缘层和第二绝缘层彼此接触。