公开(公告)号：US09859290B1

公开(公告)日：2018-01-02

申请号：US15342098

申请日：2016-11-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Lanxiang Wang ,  Hong Liao ,  Chao Jiang ,  Bo Liu ,  Xin Xu

IPC: H01L21/336 ,  H01L27/11521 ,  H01L29/49 ,  H01L29/423 ,  H01L23/522 ,  H01L27/08 ,  H01L29/92 ,  H01L27/108 ,  H01L27/11502

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L23/485 ,  H01L23/5223 ,  H01L27/0805 ,  H01L27/10852 ,  H01L27/11502 ,  H01L28/55 ,  H01L29/42324 ,  H01L29/4966 ,  H01L29/92 ,  H01L2924/30105

Abstract: A method for fabricating memory device includes the steps of: providing a substrate; forming a tunnel oxide layer on the substrate; forming a first gate layer on the tunnel oxide layer; forming a negative capacitance (NC) insulating layer on the first gate layer; and forming a second gate layer on the NC insulating layer. Preferably, the second gate layer further includes a work function metal layer on the NC insulating layer and a low resistance metal layer on the work function metal layer.

公开(公告)号：US09331200B1

公开(公告)日：2016-05-03

申请号：US14590008

申请日：2015-01-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Lanxiang Wang ,  Hong Liao ,  Chao Jiang ,  Duan Quan Liao ,  Ye Chao Li

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/161 ,  H01L29/45

CPC classification number: H01L29/7848 ,  H01L29/161 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66568 ,  H01L29/66636

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon; and forming a first epitaxial layer, a second epitaxial layer, and a silicide layer in the substrate adjacent to the gate structure. Preferably, the first epitaxial layer, the second epitaxial layer, and the silicide layer comprise SiGeSn.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有栅极结构的衬底; 以及在与栅极结构相邻的衬底中形成第一外延层，第二外延层和硅化物层。 优选地，第一外延层，第二外延层和硅化物层包括SiGeSn。

公开(公告)号：US09911847B1

公开(公告)日：2018-03-06

申请号：US15647286

申请日：2017-07-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hock Chun Chin ,  Lanxiang Wang ,  Hong Liao ,  Chao Jiang ,  Chow Yee Lim

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/78391 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/28291 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/7881 ,  H01L29/792

Abstract: A non-volatile memory device includes a substrate, a gate stack structure, an erase gate structure, and a ferroelectric layer. The gate stack structure is disposed on the substrate. The erase gate structure is disposed on the substrate and disposed at a first side of the gate stack structure. The ferroelectric layer is disposed on a sidewall of the gate stack structure, and the ferroelectric layer is disposed between the gate stack structure and the erase gate structure. The ferroelectric layer disposed between the gate stack structure and the erase gate structure may be used to forma negative capacitance effect for amplifying the voltage applied to the erase gate structure. The purpose of reducing power consumption may be achieved accordingly.

公开(公告)号：US09847351B2

公开(公告)日：2017-12-19

申请号：US15006123

申请日：2016-01-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Lanxiang Wang ,  Hong Liao ,  Chao Jiang

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L21/77

CPC classification number: H01L27/1225 ,  H01L21/77 ,  H01L27/1218 ,  H01L27/127 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78603 ,  H01L2021/775

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region; forming a gate layer on the substrate; forming a first gate dielectric layer on the gate layer; forming a first channel layer on the first region and a second channel layer on the second region; and forming a first source/drain on the first channel layer and a second source/drain on the second channel layer.