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公开(公告)号：US20090051469A1
公开(公告)日：2009-02-26
申请号：US12260254
申请日：2008-10-29
申请人： Uei-Ming Jow , Chang-Sheng Chen , Chin-Sun Shyu , Min-Lin Lee , Shinn-Juh Lay , Ying-Jiunn Lai
发明人： Uei-Ming Jow , Chang-Sheng Chen , Chin-Sun Shyu , Min-Lin Lee , Shinn-Juh Lay , Ying-Jiunn Lai
IPC分类号： H01P1/00
CPC分类号： H01L23/14 , H01F17/0006 , H01F41/046 , H01F2017/0066 , H01G4/30 , H01G4/40 , H01L23/49811 , H01L23/49822 , H01L23/49833 , H01L23/49894 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H05K1/162 , H05K1/165 , H05K3/4626 , H05K3/4652 , H05K3/4655 , H05K3/4688 , H05K2201/0187 , H05K2201/086 , H05K2201/09672 , H01L2924/00
摘要： A multi-functional composite substrate structure is provided. The first substrate with high dielectric constant and the second substrate with low dielectric constant and low loss tangent are interlaced above the third substrate. One or more permeance blocks may be formed above each substrate, so that one or more inductors may be fabricated thereon. One or more capacitors may be fabricated on the first substrate. Also, one or more signal transmission traces of the system impedance are formed on the second substrate of the outside layer. Therefore, the inductance of the inductor(s) is effectively enhanced. Moreover, the area of built-in components is reduced. Furthermore, it has shorter delay time, smaller dielectric loss, and better return loss for the transmission of high speed and high frequency signal.
摘要翻译： 提供了多功能复合基板结构。 具有高介电常数的第一衬底和具有低介电常数和低损耗角正切的第二衬底交错在第三衬底之上。 可以在每个衬底上方形成一个或多个磁导块，从而可以在其上制造一个或多个电感器。 可以在第一基板上制造一个或多个电容器。 此外，系统阻抗的一个或多个信号传输迹线形成在外层的第二基板上。 因此，有效地提高了电感器的电感。 此外，内置组件的面积减少。 此外，它具有更短的延迟时间，更小的介电损耗和更高的传输高速和高频信号的回波损耗。
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公开(公告)号：US20080093113A1
公开(公告)日：2008-04-24
申请号：US11861297
申请日：2007-09-26
申请人： Uei-Ming Jow , Min-Lin Lee , Shinn-Juh Lay , Chin-Sun Shyu , Chang-Sheng Chen , Ying-Jiunn Lai
发明人： Uei-Ming Jow , Min-Lin Lee , Shinn-Juh Lay , Chin-Sun Shyu , Chang-Sheng Chen , Ying-Jiunn Lai
IPC分类号： H05K1/16
CPC分类号： H05K1/167 , H05K1/0224 , H05K1/025 , H05K1/0298 , H05K2201/0792 , H05K2201/09681 , H05K2201/0969
摘要： A complementary mirror image embedded planar resistor architecture is provided. In the architecture, a complementary hollow structure is formed on a ground plane or an electrode plane to minimize the parasitic resistance, so as to efficiently enhance the application frequency. In addition, in some cases, some signal transmission lines pass through the position below the embedded planar resistor, and if there is no shield at all, serious interference or cross talk phenomenon occurs. Therefore, the complementary hollow structure of the ground plane, the electrode plane, or a power layer adjacent to the embedded planar resistor is designed to be a mesh structure, so as to reduce the interference or cross talk phenomenon. In this manner, the whole resistor structure has preferable high frequency electrical characteristic in the circuit.
摘要翻译： 提供了一种互补镜像嵌入式平面电阻架构。 在该结构中，在接地平面或电极平面上形成互补的中空结构以最小化寄生电阻，从而有效地提高施加频率。 此外，在某些情况下，一些信号传输线通过嵌入式平面电阻器下方的位置，如果根本没有屏蔽，则会发生严重的干扰或串扰现象。 因此，将接地平面，电极平面或与嵌入式平面电阻器相邻的功率层的互补空心结构设计为网格结构，以减少干扰或串扰现象。 以这种方式，整个电阻器结构在电路中具有优选的高频电特性。
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公开(公告)号：US08174840B2
公开(公告)日：2012-05-08
申请号：US12260254
申请日：2008-10-29
申请人： Uei-Ming Jow , Chang-Sheng Chen , Chin-Sun Shyu , Min-Lin Lee , Shinn-Juh Lay , Ying-Jiunn Lai
发明人： Uei-Ming Jow , Chang-Sheng Chen , Chin-Sun Shyu , Min-Lin Lee , Shinn-Juh Lay , Ying-Jiunn Lai
IPC分类号： H05K1/16
CPC分类号： H01L23/14 , H01F17/0006 , H01F41/046 , H01F2017/0066 , H01G4/30 , H01G4/40 , H01L23/49811 , H01L23/49822 , H01L23/49833 , H01L23/49894 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H05K1/162 , H05K1/165 , H05K3/4626 , H05K3/4652 , H05K3/4655 , H05K3/4688 , H05K2201/0187 , H05K2201/086 , H05K2201/09672 , H01L2924/00
摘要： A multi-functional composite substrate structure is provided. The first substrate with high dielectric constant and the second substrate with low dielectric constant and low loss tangent are interlaced above the third substrate. One or more permeance blocks may be formed above each substrate, so that one or more inductors may be fabricated thereon. One or more capacitors may be fabricated on the first substrate. Also, one or more signal transmission traces of the system impedance are formed on the second substrate of the outside layer. Therefore, the inductance of the inductor(s) is effectively enhanced. Moreover, the area of built-in components is reduced. Furthermore, it has shorter delay time, smaller dielectric loss, and better return loss for the transmission of high speed and high frequency signal.
摘要翻译： 提供了多功能复合基板结构。 具有高介电常数的第一衬底和具有低介电常数和低损耗角正切的第二衬底交错在第三衬底之上。 一个或多个导磁块可以形成在每个衬底之上，使得可以在其上制造一个或多个电感器。 可以在第一基板上制造一个或多个电容器。 此外，系统阻抗的一个或多个信号传输迹线形成在外层的第二基板上。 因此，有效地提高了电感器的电感。 此外，内置组件的面积减少。 此外，它具有更短的延迟时间，更小的介电损耗和更高的传输高速和高频信号的回波损耗。
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公开(公告)号：US08035036B2
公开(公告)日：2011-10-11
申请号：US11861297
申请日：2007-09-26
申请人： Uei-Ming Jow , Min-Lin Lee , Shinn-Juh Lay , Chin-Sun Shyu , Chang-Sheng Chen , Ying-Jiunn Lai
发明人： Uei-Ming Jow , Min-Lin Lee , Shinn-Juh Lay , Chin-Sun Shyu , Chang-Sheng Chen , Ying-Jiunn Lai
IPC分类号： H05K1/16
CPC分类号： H05K1/167 , H05K1/0224 , H05K1/025 , H05K1/0298 , H05K2201/0792 , H05K2201/09681 , H05K2201/0969
摘要： A complementary mirror image embedded planar resistor architecture is provided. In the architecture, a complementary hollow structure is formed on a ground plane or an electrode plane to minimize the parasitic resistance, so as to efficiently enhance the application frequency. In addition, in some cases, some signal transmission lines pass through the position below the embedded planar resistor, and if there is no shield at all, serious interference or cross talk phenomenon occurs. Therefore, the complementary hollow structure of the ground plane, the electrode plane, or a power layer adjacent to the embedded planar resistor is designed to be a mesh structure, so as to reduce the interference or cross talk phenomenon. In this manner, the whole resistor structure has preferable high frequency electrical characteristic in the circuit.
摘要翻译： 提供了一种互补镜像嵌入式平面电阻架构。 在该结构中，在接地平面或电极平面上形成互补的中空结构以最小化寄生电阻，从而有效地提高施加频率。 此外，在某些情况下，一些信号传输线通过嵌入式平面电阻器下方的位置，如果根本没有屏蔽，则会发生严重的干扰或串扰现象。 因此，将接地平面，电极平面或与嵌入式平面电阻器相邻的功率层的互补空心结构设计为网格结构，以减少干扰或串扰现象。 以这种方式，整个电阻器结构在电路中具有优选的高频电特性。
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公开(公告)号：US20070164396A1
公开(公告)日：2007-07-19
申请号：US11646339
申请日：2006-12-28
申请人： Uei-Ming Jow , Chang-Sheng Chen , Chin-Sun Shyu , Min-Lin Lee , Shinn-Juh Lay , Ying-Jiunn Lai
发明人： Uei-Ming Jow , Chang-Sheng Chen , Chin-Sun Shyu , Min-Lin Lee , Shinn-Juh Lay , Ying-Jiunn Lai
IPC分类号： H01L29/00
CPC分类号： H01L23/14 , H01F17/0006 , H01F41/046 , H01F2017/0066 , H01G4/30 , H01G4/40 , H01L23/49811 , H01L23/49822 , H01L23/49833 , H01L23/49894 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H05K1/162 , H05K1/165 , H05K3/4626 , H05K3/4652 , H05K3/4655 , H05K3/4688 , H05K2201/0187 , H05K2201/086 , H05K2201/09672 , H01L2924/00
摘要： A multi-functional composite substrate structure is provided. The first substrate with high dielectric constant and the second substrate with low dielectric constant and low loss tangent are interlaced above the third substrate. One or more permeance blocks may be formed above each substrate, so that one or more inductors may be fabricated thereon. One or more capacitors may be fabricated on the first substrate. Also, one or more signal transmission traces of the system impedance are formed on the second substrate of the outside layer. Therefore, the inductance of the inductor(s) is effectively enhanced. Moreover, the area of built-in components is reduced. Furthermore, it has shorter delay time, smaller dielectric loss, and better return loss for the transmission of high speed and high frequency signal.
摘要翻译： 提供了多功能复合基板结构。 具有高介电常数的第一衬底和具有低介电常数和低损耗角正切的第二衬底交错在第三衬底之上。 一个或多个导磁块可以形成在每个衬底之上，使得可以在其上制造一个或多个电感器。 可以在第一基板上制造一个或多个电容器。 此外，系统阻抗的一个或多个信号传输迹线形成在外层的第二基板上。 因此，有效地提高了电感器的电感。 此外，内置组件的面积减少。 此外，它具有更短的延迟时间，更小的介电损耗和更高的传输高速和高频信号的回波损耗。
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公开(公告)号：US07515435B2
公开(公告)日：2009-04-07
申请号：US11646339
申请日：2006-12-28
申请人： Uei-Ming Jow , Chang-Sheng Chen , Chin-Sun Shyu , Min-Lin Lee , Shinn-Juh Lay , Ying-Jiunn Lai
发明人： Uei-Ming Jow , Chang-Sheng Chen , Chin-Sun Shyu , Min-Lin Lee , Shinn-Juh Lay , Ying-Jiunn Lai
IPC分类号： H05K1/16
CPC分类号： H01L23/14 , H01F17/0006 , H01F41/046 , H01F2017/0066 , H01G4/30 , H01G4/40 , H01L23/49811 , H01L23/49822 , H01L23/49833 , H01L23/49894 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H05K1/162 , H05K1/165 , H05K3/4626 , H05K3/4652 , H05K3/4655 , H05K3/4688 , H05K2201/0187 , H05K2201/086 , H05K2201/09672 , H01L2924/00
摘要： A multi-functional composite substrate structure is provided. The first substrate with high dielectric constant and the second substrate with low dielectric constant and low loss tangent are interlaced above the third substrate. One or more permeance blocks may be formed above each substrate, so that one or more inductors may be fabricated thereon. One or more capacitors may be fabricated on the first substrate. Also, one or more signal transmission traces of the system impedance are formed on the second substrate of the outside layer. Therefore, the inductance of the inductor(s) is effectively enhanced. Moreover, the area of built-in components is reduced. Furthermore, it has shorter delay time, smaller dielectric loss, and better return loss for the transmission of high speed and high frequency signal.
摘要翻译： 提供了多功能复合基板结构。 具有高介电常数的第一衬底和具有低介电常数和低损耗角正切的第二衬底交错在第三衬底之上。 可以在每个衬底上方形成一个或多个磁导块，从而可以在其上制造一个或多个电感器。 可以在第一基板上制造一个或多个电容器。 此外，系统阻抗的一个或多个信号传输迹线形成在外层的第二基板上。 因此，有效地提高了电感器的电感。 此外，内置组件的面积减少。 此外，它具有更短的延迟时间，更小的介电损耗和更高的传输高速和高频信号的回波损耗。
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公开(公告)号：US20070152339A1
公开(公告)日：2007-07-05
申请号：US11708935
申请日：2007-02-20
申请人： Uei-Ming Jow , Min-Lin Lee , Shinn-Juh Lay , Chin-Sun Shyu , Chang-Sheng Chen
发明人： Uei-Ming Jow , Min-Lin Lee , Shinn-Juh Lay , Chin-Sun Shyu , Chang-Sheng Chen
IPC分类号： H01L21/00 , H01L21/4763
CPC分类号： H05K1/0268 , G01R31/2818 , H05K1/0298 , H05K1/116 , H05K1/162 , H05K1/165 , H05K1/167
摘要： A method is provided for testing a built-in component including multiple terminals in a multi-layered circuit board. At least one signal pad is provided on a top surface of the multi-layered circuit board for signal transmission. Each of the signal pads are electrically connected to one of the multiple terminals. At least one test pad is provided on the top surface of the multi-layered circuit board and each of the test pads is electrically connected to one of the multiple terminals. Then, detection occurs regarding one of the signal pads and one of the test pads that are electrically connected to a same one of the multiple terminals in order to determine a connection status of an electric path extending from the one signal pad through the same one terminal to the one test pad.
摘要翻译： 提供一种用于在多层电路板中测试包括多个端子的内置组件的方法。 在用于信号传输的多层电路板的顶表面上提供至少一个信号焊盘。 每个信号焊盘电连接到多个端子中的一个。 在多层电路板的顶表面上提供至少一个测试焊盘，并且每个测试焊盘电连接到多个端子之一。 然后，对于电连接到多个端子中的一个的一个信号焊盘和测试焊盘之一进行检测，以便确定从一个信号焊盘延伸通过相同的一个端子的电通路的连接状态 到一个测试垫。
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公开(公告)号：US07714590B2
公开(公告)日：2010-05-11
申请号：US11708935
申请日：2007-02-20
申请人： Uei-Ming Jow , Min-Lin Lee , Shinn-Juh Lay , Chin-Sun Shyu , Chang-Sheng Chen
发明人： Uei-Ming Jow , Min-Lin Lee , Shinn-Juh Lay , Chin-Sun Shyu , Chang-Sheng Chen
CPC分类号： H05K1/0268 , G01R31/2818 , H05K1/0298 , H05K1/116 , H05K1/162 , H05K1/165 , H05K1/167
摘要： A method is provided for testing a built-in component including multiple terminals in a multi-layered circuit board. At least one signal pad is provided on a top surface of the multi-layered circuit board for signal transmission. Each of the signal pads are electrically connected to one of the multiple terminals. At least one test pad is provided on the top surface of the multi-layered circuit board and each of the test pads is electrically connected to one of the multiple terminals. Then, detection occurs regarding one of the signal pads and one of the test pads that are electrically connected to a same one of the multiple terminals in order to determine a connection status of an electric path extending from the one signal pad through the same one terminal to the one test pad.
摘要翻译： 提供一种用于在多层电路板中测试包括多个端子的内置组件的方法。 在用于信号传输的多层电路板的顶表面上提供至少一个信号焊盘。 每个信号焊盘电连接到多个端子中的一个。 在多层电路板的顶表面上提供至少一个测试焊盘，并且每个测试焊盘电连接到多个端子之一。 然后，对于电连接到多个端子中的一个的一个信号焊盘和测试焊盘之一进行检测，以便确定从一个信号焊盘延伸通过相同的一个端子的电通路的连接状态 到一个测试垫。
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公开(公告)号：US07345366B2
公开(公告)日：2008-03-18
申请号：US11131741
申请日：2005-05-18
申请人： Uei-Ming Jow , Min-Lin Lee , Shinn-Juh Lay , Chin-Sun Shyu , Chang-Sheng Chen
发明人： Uei-Ming Jow , Min-Lin Lee , Shinn-Juh Lay , Chin-Sun Shyu , Chang-Sheng Chen
CPC分类号： H05K1/0268 , G01R31/2818 , H05K1/0298 , H05K1/116 , H05K1/162 , H05K1/165 , H05K1/167
摘要： A multi-layered circuit board a built-in component including multiple terminals, at least one signal pad formed on a top surface of the multi-layered circuit board for signal transmission, each of the at least one signal pad corresponding to one of the multiple terminals, and at least one test pad formed on the top surface of the multi-layered circuit board, each of the at least one test pad corresponding to one of the at least one signal pad for testing an electric path extending from the one signal pad through the one terminal to the each of the at least one test pad.
摘要翻译： 一种多层电路板，包括多个端子的内置组件，至少一个形成在用于信号传输的多层电路板的顶表面上的信号焊盘，所述至少一个信号焊盘中的每一个对应于多个 端子和形成在多层电路板的顶表面上的至少一个测试焊盘，所述至少一个测试焊盘中的每一个对应于至少一个信号焊盘中的一个，用于测试从一个信号焊盘延伸的电路径 通过所述一个端子到所述至少一个测试垫中的每一个。
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公开(公告)号：US20060261482A1
公开(公告)日：2006-11-23
申请号：US11131741
申请日：2005-05-18
申请人： Uei-Ming Jow , Min-Lin Lee , Shinn-Juh Lay , Chin-Sun Shyu , Chang-Sheng Chen
发明人： Uei-Ming Jow , Min-Lin Lee , Shinn-Juh Lay , Chin-Sun Shyu , Chang-Sheng Chen
IPC分类号： H01L23/52
CPC分类号： H05K1/0268 , G01R31/2818 , H05K1/0298 , H05K1/116 , H05K1/162 , H05K1/165 , H05K1/167
摘要： A multi-layered circuit board a built-in component including multiple terminals, at least one signal pad formed on a top surface of the multi-layered circuit board for signal transmission, each of the at least one signal pad corresponding to one of the multiple terminals, and at least one test pad formed on the top surface of the multi-layered circuit board, each of the at least one test pad corresponding to one of the at least one signal pad for testing an electric path extending from the one signal pad through the one terminal to the each of the at least one test pad.
摘要翻译： 一种多层电路板，包括多个端子的内置组件，至少一个形成在用于信号传输的多层电路板的顶表面上的信号焊盘，所述至少一个信号焊盘中的每一个对应于多个 端子和形成在多层电路板的顶表面上的至少一个测试焊盘，所述至少一个测试焊盘中的每一个对应于至少一个信号焊盘中的一个，用于测试从一个信号焊盘延伸的电路径 通过所述一个端子到所述至少一个测试垫中的每一个。
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