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公开(公告)号：US20180354783A1
公开(公告)日：2018-12-13
申请号：US16107795
申请日：2018-08-21
Applicant: United Microelectronics Corp.
Inventor： Chang-Sheng Hsu , Chih-Fan Hu , Chia-Wei Lee , En Chan Chen , Shih-Wei Li
IPC: B81C1/00
CPC classification number: B81C1/00246 , B81B2207/015 , B81B2207/07 , B81C2201/0176 , B81C2203/036 , B81C2203/0735
Abstract: A microelectromechanical system structure and a method for fabricating the same are provided. A method for fabricating a MEMS structure includes the following steps. A first substrate is provided, wherein a transistor, a first dielectric layer and an interconnection structure are formed thereon. A second substrate is provided, wherein a second dielectric layer and a thermal stability layer are formed on the second substrate. The first substrate is bonded to the second substrate, and the second substrate removed. A conductive layer is formed within the second dielectric layer and electrically connected to the interconnection structure. The thermal stability layer is located between the conductive layer and the interconnection structure. A growth temperature of a material of the thermal stability layer is higher than a growth temperature of a material of the conductive layer and a growth temperature of a material of the interconnection structure.
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公开(公告)号：US20180339901A1
公开(公告)日：2018-11-29
申请号：US15644430
申请日：2017-07-07
Applicant: United Microelectronics Corp.
Inventor： Guo-Chih Wei , Weng-Yi Chen , Shih-Wei Li
IPC: B81C1/00
Abstract: A semiconductor process including the following steps is provided. A wafer is provided. The wafer has a front side and a back side. The wafer has a semiconductor device on the front side. A protection layer is formed on the front side of the wafer. The protection layer covers the semiconductor device. A material of the protection layer includes a photoresist material. A surface hardening treatment process is performed on the protection layer. A first patterning process is performed on the back side of the wafer. The semiconductor process can effectively protect the front side of the wafer during a backside process.
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公开(公告)号：US20180027337A1
公开(公告)日：2018-01-25
申请号：US15246561
申请日：2016-08-25
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chang-Sheng Hsu , Weng-Yi Chen , En-Chan Chen , Shih-Wei Li , Guo-Chih Wei
CPC classification number: H04R17/025 , B81B3/0021 , B81B2201/0257 , B81B2203/0127 , B81B2203/0315 , B81C1/00158 , B81C2201/013 , H04R1/06 , H04R7/04 , H04R7/20 , H04R17/02 , H04R19/005 , H04R31/003 , H04R31/006 , H04R2201/003
Abstract: A piezoresistive microphone includes a substrate, an insulating layer, and a polysilicon layer. A first pattern is disposed within the polysilicon layer. The first pattern includes numerous first opening. A second pattern is disposed within the polysilicon layer. The second pattern includes numerous second openings. The first pattern surrounds the second pattern. Each first opening and each second opening are staggered. A first resistor is disposed in the polysilicon and between the first pattern and the second pattern. The first resistor is composed of numerous first heavily doped regions and numerous first lightly doped regions. The first heavily doped regions and the first lightly doped regions are disposed in series. The first heavily doped region and the first lightly doped region are disposed alternately. A cavity is disposed in the insulating layer and the substrate.
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公开(公告)号：US20170362081A1
公开(公告)日：2017-12-21
申请号：US15697467
申请日：2017-09-07
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Meng-Jia Lin , Yung-Hsiao Lee , Weng-Yi Chen , Shih-Wei Li , Chung-Hsien Liu
Abstract: A method of fabricating a MEMS structure includes providing a substrate comprising a logic element region and a MEMS region. Next, a logic element is formed within the logic element region. A nitrogen-containing material layer is formed to cover the logic element region and the MEMS region conformally. Then, part of the nitrogen-containing material layer within the MEMS region is removed to form at least one shrinking region. Subsequently, a dielectric layer is formed to cover the logic element region and MEMS region, and the dielectric layer fills in the shrinking region. After that, the dielectric layer is etched to form at least one releasing hole, wherein the shrinking region surrounds the releasing hole. Finally, the substrate is etched to form a chamber.
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公开(公告)号：US10773953B2
公开(公告)日：2020-09-15
申请号：US15697467
申请日：2017-09-07
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Meng-Jia Lin , Yung-Hsiao Lee , Weng-Yi Chen , Shih-Wei Li , Chung-Hsien Liu
Abstract: A method of fabricating a MEMS structure includes providing a substrate comprising a logic element region and a MEMS region. Next, a logic element is formed within the logic element region. A nitrogen-containing material layer is formed to cover the logic element region and the MEMS region conformally. Then, part of the nitrogen-containing material layer within the MEMS region is removed to form at least one shrinking region. Subsequently, a dielectric layer is formed to cover the logic element region and MEMS region, and the dielectric layer fills in the shrinking region. After that, the dielectric layer is etched to form at least one releasing hole, wherein the shrinking region surrounds the releasing hole. Finally, the substrate is etched to form a chamber.
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Patent Agency Ranking
公开(公告)号：US10087072B2
公开(公告)日：2018-10-02
申请号：US15146741
申请日：2016-05-04
Applicant: United Microelectronics Corp.
Inventor： Chang-Sheng Hsu , Chih-Fan Hu , Chia-Wei Lee , En Chan Chen , Shih-Wei Li
IPC: H01L23/48 , H01L23/528 , H01L23/66 , H01L29/66 , B81C1/00
Abstract: A microelectromechanical system structure and a method for fabricating the same are provided. A method for fabricating a MEMS structure includes the following steps. A first substrate is provided, wherein a transistor, a first dielectric layer and an interconnection structure are formed thereon. A second substrate is provided, wherein a second dielectric layer and a thermal stability layer are formed on the second substrate. The first substrate is bonded to the second substrate, and the second substrate removed. A conductive layer is formed within the second dielectric layer and electrically connected to the interconnection structure. The thermal stability layer is located between the conductive layer and the interconnection structure. A growth temperature of a material of the thermal stability layer is higher than a growth temperature of a material of the conductive layer and a growth temperature of a material of the interconnection structure.
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公开(公告)号：US09961450B2
公开(公告)日：2018-05-01
申请号：US15246561
申请日：2016-08-25
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chang-Sheng Hsu , Weng-Yi Chen , En-Chan Chen , Shih-Wei Li , Guo-Chih Wei
CPC classification number: H04R17/025 , B81B3/0021 , B81B2201/0257 , B81B2203/0127 , B81B2203/0315 , B81C1/00158 , B81C2201/013 , H04R1/06 , H04R7/04 , H04R7/20 , H04R17/02 , H04R19/005 , H04R31/003 , H04R31/006 , H04R2201/003
Abstract: A piezoresistive microphone includes a substrate, an insulating layer, and a polysilicon layer. A first pattern is disposed within the polysilicon layer. The first pattern includes numerous first opening. A second pattern is disposed within the polysilicon layer. The second pattern includes numerous second openings. The first pattern surrounds the second pattern. Each first opening and each second opening are staggered. A first resistor is disposed in the polysilicon and between the first pattern and the second pattern. The first resistor is composed of numerous first heavily doped regions and numerous first lightly doped regions. The first heavily doped regions and the first lightly doped regions are disposed in series. The first heavily doped region and the first lightly doped region are disposed alternately. A cavity is disposed in the insulating layer and the substrate.
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公开(公告)号：US09790088B2
公开(公告)日：2017-10-17
申请号：US14993105
申请日：2016-01-12
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Meng-Jia Lin , Yung-Hsiao Lee , Weng-Yi Chen , Shih-Wei Li , Chung-Hsien Liu
CPC classification number: B81C1/00246 , B81B7/008 , B81B2201/0235 , B81B2201/0285 , B81B2203/0315 , B81B2207/012 , B81B2207/015 , B81C1/00571 , B81C2201/0132 , B81C2201/014
Abstract: A method of fabricating a MEMS structure includes providing a substrate comprising a logic element region and a MEMS region. Next, a logic element is formed within the logic element region. A nitrogen-containing material layer is formed to cover the logic element region and the MEMS region conformally. Then, part of the nitrogen-containing material layer within the MEMS region is removed to form at least one shrinking region. Subsequently, a dielectric layer is formed to cover the logic element region and MEMS region, and the dielectric layer fills in the shrinking region. After that, the dielectric layer is etched to form at least one releasing hole, wherein the shrinking region surrounds the releasing hole. Finally, the substrate is etched to form a chamber.
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公开(公告)号：US20170166441A1
公开(公告)日：2017-06-15
申请号：US14993105
申请日：2016-01-12
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Meng-Jia Lin , Yung-Hsiao Lee , Weng-Yi Chen , Shih-Wei Li , Chung-Hsien Liu
CPC classification number: B81C1/00246 , B81B7/008 , B81B2201/0235 , B81B2201/0285 , B81B2203/0315 , B81B2207/012 , B81B2207/015 , B81C1/00571 , B81C2201/0132 , B81C2201/014
Abstract: A method of fabricating a MEMS structure includes providing a substrate comprising a logic element region and a MEMS region. Next, a logic element is formed within the logic element region. A nitrogen-containing material layer is formed to cover the logic element region and the MEMS region conformally. Then, part of the nitrogen-containing material layer within the MEMS region is removed to form at least one shrinking region. Subsequently, a dielectric layer is formed to cover the logic element region and MEMS region, and the dielectric layer fills in the shrinking region. After that, the dielectric layer is etched to form at least one releasing hole, wherein the shrinking region surrounds the releasing hole. Finally, the substrate is etched to form a chamber.
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公开(公告)号：US20160229692A1
公开(公告)日：2016-08-11
申请号：US14643183
申请日：2015-03-10
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yuan-Sheng Lin , Chang-Sheng Hsu , Meng-Jia Lin , Shih-Wei Li , Yan-Da Chen
CPC classification number: B81C1/00238 , B81B2203/0127 , B81C2203/0792
Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a base substrate and a MEMS structure. The base substrate comprises a CMOS structure. The MEMS structure is formed on the base substrate adjacent to the CMOS structure. The MEMS structure is connected to the CMOS structure. The MEMS structure comprises a membrane and a backplate. The base substrate has a cavity corresponding to the MEMS structure.
Abstract translation: 提供半导体结构及其制造方法。 半导体结构包括基底和MEMS结构。 基底包括CMOS结构。 MEMS结构形成在与CMOS结构相邻的基底基板上。 MEMS结构连接到CMOS结构。 MEMS结构包括膜和背板。 基底衬底具有对应于MEMS结构的空腔。
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