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    MEMS structure and method of fabricating the same
    2.
    发明授权
    MEMS structure and method of fabricating the same 有权

    公开(公告)号：US10773953B2

    公开(公告)日：2020-09-15

    申请号：US15697467

    申请日：2017-09-07

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Meng-Jia Lin ,  Yung-Hsiao Lee ,  Weng-Yi Chen ,  Shih-Wei Li ,  Chung-Hsien Liu

    IPC: B81C1/00 ,  B81B7/00

    Abstract: A method of fabricating a MEMS structure includes providing a substrate comprising a logic element region and a MEMS region. Next, a logic element is formed within the logic element region. A nitrogen-containing material layer is formed to cover the logic element region and the MEMS region conformally. Then, part of the nitrogen-containing material layer within the MEMS region is removed to form at least one shrinking region. Subsequently, a dielectric layer is formed to cover the logic element region and MEMS region, and the dielectric layer fills in the shrinking region. After that, the dielectric layer is etched to form at least one releasing hole, wherein the shrinking region surrounds the releasing hole. Finally, the substrate is etched to form a chamber.

    SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
    6.
    发明申请
    SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
    半导体结构及其制造方法

    公开(公告)号：US20160229692A1

    公开(公告)日：2016-08-11

    申请号：US14643183

    申请日：2015-03-10

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yuan-Sheng Lin ,  Chang-Sheng Hsu ,  Meng-Jia Lin ,  Shih-Wei Li ,  Yan-Da Chen

    IPC: B81C1/00 ,  B81B3/00

    CPC classification number: B81C1/00238 ,  B81B2203/0127 ,  B81C2203/0792

    Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a base substrate and a MEMS structure. The base substrate comprises a CMOS structure. The MEMS structure is formed on the base substrate adjacent to the CMOS structure. The MEMS structure is connected to the CMOS structure. The MEMS structure comprises a membrane and a backplate. The base substrate has a cavity corresponding to the MEMS structure.

    Abstract translation: 提供半导体结构及其制造方法。 半导体结构包括基底和MEMS结构。 基底包括CMOS结构。 MEMS结构形成在与CMOS结构相邻的基底基板上。 MEMS结构连接到CMOS结构。 MEMS结构包括膜和背板。 基底衬底具有对应于MEMS结构的空腔。

    MEMS STRUCTURE AND METHOD OF FABRICATING THE SAME
    7.
    发明申请
    MEMS STRUCTURE AND METHOD OF FABRICATING THE SAME 审中-公开

    公开(公告)号：US20170362081A1

    公开(公告)日：2017-12-21

    申请号：US15697467

    申请日：2017-09-07

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Meng-Jia Lin ,  Yung-Hsiao Lee ,  Weng-Yi Chen ,  Shih-Wei Li ,  Chung-Hsien Liu

    IPC: B81C1/00 ,  B81B7/00

    Abstract: A method of fabricating a MEMS structure includes providing a substrate comprising a logic element region and a MEMS region. Next, a logic element is formed within the logic element region. A nitrogen-containing material layer is formed to cover the logic element region and the MEMS region conformally. Then, part of the nitrogen-containing material layer within the MEMS region is removed to form at least one shrinking region. Subsequently, a dielectric layer is formed to cover the logic element region and MEMS region, and the dielectric layer fills in the shrinking region. After that, the dielectric layer is etched to form at least one releasing hole, wherein the shrinking region surrounds the releasing hole. Finally, the substrate is etched to form a chamber.

    Semiconductor device and method of forming the same
    8.
    发明授权
    Semiconductor device and method of forming the same 有权
    半导体器件及其形成方法

    公开(公告)号：US08981501B2

    公开(公告)日：2015-03-17

    申请号：US13870706

    申请日：2013-04-25

    Applicant: United Microelectronics Corp.

    Inventor： Meng-Jia Lin ,  Chang-Sheng Hsu ,  Kuo-Hsiung Huang ,  Wei-Hua Fang ,  Shou-Wei Hsieh ,  Te-Yuan Wu ,  Chia-Huei Lin

    IPC: H01L29/84 ,  H01L21/311 ,  H01L23/48 ,  B81C1/00 ,  H01L27/06

    CPC classification number: H01L21/31116 ,  B81C1/00246 ,  B81C2203/0714 ,  B81C2203/0742 ,  H01L21/3065 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/0617 ,  H01L2924/0002 ,  H04R2201/003 ,  H01L2924/00

    Abstract: A method of forming a semiconductor device is disclosed. Provided is a substrate having at least one MOS device, at least one metal interconnection and at least one MOS device formed on a first surface thereof. A first anisotropic etching process is performed to remove a portion of the substrate from a second surface of the substrate and thereby form a plurality of vias in the substrate, wherein the second surface is opposite to the first surface. A second anisotropic etching process is performed to remove another portion of the substrate from the second surface of the substrate and thereby form a cavity in the substrate, wherein the remaining vias are located below the cavity. An isotropic etching process is performed to the cavity and the remaining vias.

    Abstract translation: 公开了一种形成半导体器件的方法。 提供了具有至少一个MOS器件，至少一个金属互连和至少一个MOS器件的衬底，该MOS器件形成在其第一表面上。 执行第一各向异性蚀刻工艺以从衬底的第二表面去除衬底的一部分，从而在衬底中形成多个通孔，其中第二表面与第一表面相对。 执行第二各向异性蚀刻工艺以从衬底的第二表面移除衬底的另一部分，从而在衬底中形成空腔，其中剩余的通孔位于腔的下方。 对空腔和剩余的通孔进行各向同性蚀刻工艺。

    SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
    9.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME 有权
    半导体器件及其形成方法

    公开(公告)号：US20140319693A1

    公开(公告)日：2014-10-30

    申请号：US13870706

    申请日：2013-04-25

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Meng-Jia Lin ,  Chang-Sheng Hsu ,  Kuo-Hsiung Huang ,  Wei-Hua Fang ,  Shou-Wei Hsieh ,  Te-Yuan Wu ,  Chia-Huei Lin

    IPC: H01L21/311 ,  H01L23/48

    CPC classification number: H01L21/31116 ,  B81C1/00246 ,  B81C2203/0714 ,  B81C2203/0742 ,  H01L21/3065 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/0617 ,  H01L2924/0002 ,  H04R2201/003 ,  H01L2924/00

    Abstract: A method of forming a semiconductor device is disclosed. Provided is a substrate having at least one MOS device, at least one metal interconnection and at least one MOS device formed on a first surface thereof. A first anisotropic etching process is performed to remove a portion of the substrate from a second surface of the substrate and thereby form a plurality of vias in the substrate, wherein the second surface is opposite to the first surface. A second anisotropic etching process is performed to remove another portion of the substrate from the second surface of the substrate and thereby form a cavity in the substrate, wherein the remaining vias are located below the cavity. An isotropic etching process is performed to the cavity and the remaining vias.

    Abstract translation: 公开了一种形成半导体器件的方法。 提供了具有至少一个MOS器件，至少一个金属互连和至少一个MOS器件的衬底，该MOS器件形成在其第一表面上。 执行第一各向异性蚀刻工艺以从衬底的第二表面去除衬底的一部分，从而在衬底中形成多个通孔，其中第二表面与第一表面相对。 执行第二各向异性蚀刻工艺以从衬底的第二表面移除衬底的另一部分，从而在衬底中形成空腔，其中剩余的通孔位于腔的下方。 对空腔和剩余的通孔进行各向同性蚀刻工艺。

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