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    Optical add/drop interconnect bus for multiprocessor architecture
    1.
    发明申请
    Optical add/drop interconnect bus for multiprocessor architecture 有权
    用于多处理器架构的光分插互连总线

    公开(公告)号：US20050276604A1

    公开(公告)日：2005-12-15

    申请号：US10868571

    申请日：2004-06-15

    申请人： Warren Morrow ,  Brandon Barnett

    发明人： Warren Morrow ,  Brandon Barnett

    IPC分类号： H04J14/00 ,  H04J14/02

    CPC分类号： H04J14/0227 ,  H04J14/0201 ,  H04J14/0241 ,  H04J14/028

    摘要： An optical bus interconnects two or more processors in a multiprocessor system. One or more electrical-to-optical (“E-O”) transmitters are optically coupled to the optical bus using optical couplers. The E-O transmitters receive electrical signals from the processors and convert the electrical signals to optical signals to be guided onto the optical bus. Optical-to-electrical (“O-E”) receivers are also coupled to the optical bus using the optical couplers. The O-E receivers receive optical signals from the optical bus and convert the optical signals to electrical signals for the processors.

    摘要翻译： 光总线在多处理器系统中互连两个或多个处理器。 一个或多个电对光（“E-O”）发射器使用光耦合器光耦合到光总线。 E-O发射机接收来自处理器的电信号，并将电信号转换为光信号以引导到光总线上。 光 - 电（“O-E”）接收器也使用光耦合器耦合到光总线。 O-E接收器从光总线接收光信号，并将光信号转换为处理器的电信号。

    Low latency optical memory bus
    2.
    发明申请
    Low latency optical memory bus 审中-公开
    低延迟光存储器总线

    公开(公告)号：US20050147414A1

    公开(公告)日：2005-07-07

    申请号：US10748758

    申请日：2003-12-30

    申请人： Warren Morrow ,  Brandon Barnett

    发明人： Warren Morrow ,  Brandon Barnett

    IPC分类号： G02B6/43 ,  G06F13/16 ,  H04B10/12

    CPC分类号： G06F13/1668

    摘要： Embodiments of the present invention include an integrated circuit to communicate with a memory device. The integrated circuit includes an optical transmitter and an optical bus coupled to the integrated circuit's optical transmitter. N optical receivers are coupled to the optical bus via N optical couplers. N memory modules are coupled to the N optical receivers. M memory devices are coupled to the N memory modules. The optical transmitter converts a signal to communicate with the N memory modules from an electrical signal to an optical signal. The optical bus propagates the optical signal. Each of the N optical couplers to couple a one-Nth of the optical signal from the optical bus to each one of the N optical receivers, each of the N optical receivers converts its one-Nth of the optical signal to an electrical signal for its associated memory device.

    摘要翻译： 本发明的实施例包括与存储器件通信的集成电路。 集成电路包括耦合到集成电路的光发射机的光发射机和光总线。 N个光接收器通过N个光耦合器耦合到光总线。 N个存储器模块耦合到N个光接收器。 M个存储器件耦合到N个存储器模块。 光发射机将信号与N个存储器模块从电信号转换为光信号。 光总线传播光信号。 N个光耦合器中的每一个用于将来自光总线的光信号的1/9​​耦合到N个光接收器中的每一个，N个光接收器中的每一个将其光信号的1/9​​转换为其电信号 关联的存储设备。

    Memory controllers with interleaved mirrored memory modes
    5.
    发明申请
    Memory controllers with interleaved mirrored memory modes 有权
    具有交错镜像存储器模式的存储器控​​制器

    公开(公告)号：US20050262388A1

    公开(公告)日：2005-11-24

    申请号：US11181583

    申请日：2005-07-14

    申请人： Eric Dahlen ,  Warren Morrow ,  Peter Vogt

    发明人： Eric Dahlen ,  Warren Morrow ,  Peter Vogt

    IPC分类号： G06F11/20 ,  G06F12/00 ,  G06F12/02 ,  G06F12/12 ,  G06F12/16 ,  G11C5/00 ,  G11C29/00

    CPC分类号： G06F11/2061 ,  G06F11/2069 ,  G06F11/2087 ,  G11C8/04

    摘要： In some embodiments, a memory controller includes first and second memory channel interfaces and memory access control circuitry. The memory access control circuitry is to send first and second primary data sections to the first and second memory channel interfaces, respectively, and send first and second redundant data sections to the second and first memory channel interfaces, respectively. The first and second redundant data sections are redundant with respect to the first and second primary data sections, respectively. Other embodiments are described and claimed.

    摘要翻译： 在一些实施例中，存储器控制器包括第一和第二存储器通道接口和存储器访问控制电路。 存储器访问控制电路分别将第一和第二主数据段发送到第一和第二存储器通道接口，并且分别向第二和第一存储器通道接口发送第一和第二冗余数据段。 第一和第二冗余数据部分分别相对于第一和第二主数据部分是冗余的。 描述和要求保护其他实施例。

    STACKED MEMORY WITH INTERFACE PROVIDING OFFSET INTERCONNECTS
    6.
    发明申请
    STACKED MEMORY WITH INTERFACE PROVIDING OFFSET INTERCONNECTS 有权
    具有接口的堆叠存储器提供偏移互连

    公开(公告)号：US20130272049A1

    公开(公告)日：2013-10-17

    申请号：US13997148

    申请日：2011-12-02

    申请人： Pete Vogt ,  Andre Schaefer ,  Warren Morrow ,  John Halbert ,  Jin Kim ,  Kenneth Shoemaker

    发明人： Pete Vogt ,  Andre Schaefer ,  Warren Morrow ,  John Halbert ,  Jin Kim ,  Kenneth Shoemaker

    IPC分类号： G11C5/06 ,  H01L23/48

    CPC分类号： H01L25/0657 ,  G11C5/06 ,  H01L23/481 ,  H01L24/16 ,  H01L27/108 ,  H01L27/10882 ,  H01L27/10897 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541

    摘要： Dynamic operations for operations for a stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.

    摘要翻译： 用于具有提供偏移互连的接口的堆叠存储器的操作的动态操作。 存储器件的实施例包括与系统元件耦合的系统元件和存储器堆栈，存储器堆栈包括一个或多个存储器管芯层。 每个存储器管芯层包括第一面和第二面，每个存储管芯层的第二面包括用于将存储管芯层的数据接口引脚与耦合元件的第一面的数据接口引脚耦合的接口。 每个存储器管芯层的接口包括在存储管芯层的每个数据接口引脚和耦合元件的数据接口引脚的相应数据接口引脚之间提供偏移的连接。

    System and method for thermal throttling of memory modules
    9.
    发明申请
    System and method for thermal throttling of memory modules 有权
    内存模块热节流的系统和方法

    公开(公告)号：US20050289292A1

    公开(公告)日：2005-12-29

    申请号：US10881727

    申请日：2004-06-29

    申请人： Warren Morrow ,  Eric Dahlen ,  Raman Nayyar ,  Jayamohan Dharanipathi ,  Howard David

    发明人： Warren Morrow ,  Eric Dahlen ,  Raman Nayyar ,  Jayamohan Dharanipathi ,  Howard David

    IPC分类号： G06F1/20 ,  G06F12/00 ,  G06F13/16 ,  G11C5/00 ,  G11C5/14 ,  G11C7/04

    CPC分类号： G06F1/206 ,  G06F13/161 ,  G11C5/00 ,  G11C5/14 ,  G11C5/143 ,  G11C7/04

    摘要： Some embodiments of the invention accurately account for power dissipation in memory systems that include individual memory modules by keeping track of the number of read requests, the number of write requests, and the number of activate requests that are applied to the individual memory modules during selected time periods. If the sum of these totals exceeds a threshold level, the embodiments throttle the memory system, either by throttling the entire memory system based in response to the most active memory module, or by throttling individual memory modules as needed. Other embodiments of the invention may assign the same or different weights to activate requests, read requests, and write requests. Other embodiments are described and claimed.

    摘要翻译： 本发明的一些实施例通过在所选择的期间跟踪读取请求的数量，写入请求的数量和应用于各个存储器模块的激活请求的数量来准确地说明存储器系统中包括单独的存储器模块的功率消耗 时间段 如果这些总和的总和超过阈值水平，则实施例通过响应于最活跃的存储器模块来调节整个存储器系统或通过根据需要调节各个存储器模块来节制存储器系统。 本发明的其他实施例可以分配相同或不同的权重来激活请求，读请求和写请求。 描述和要求保护其他实施例。