公开(公告)号：US08569849B2

公开(公告)日：2013-10-29

申请号：US13618908

申请日：2012-09-14

申请人： Wei-Hang Huang ,  Shih-Chang Liu ,  Chern-Yow Hsu ,  Fu-Ting Sung ,  Chia-Shiung Tsai

发明人： Wei-Hang Huang ,  Shih-Chang Liu ,  Chern-Yow Hsu ,  Fu-Ting Sung ,  Chia-Shiung Tsai

IPC分类号： H01L29/82

CPC分类号： H01L43/12 ,  G11C11/16

摘要： A semiconductor device and a method of manufacture are provided, such as a MTJ device and a method of manufacturing a MTJ device. The MTJ device may include a bottom electrode, a MTJ stack, and a top electrode, wherein the top electrode is formed using a hole-filling technique. The top electrode may have slanted sidewalls. The MTJ stack may be formed by depositing corresponding MTJ layers. A patterned mask may be formed and patterned over the MTJ layers to form an opening defining the top electrode. The opening is filled with a conductive material to form the top electrode. The top electrode is then used as a mask to pattern the MTJ layers, thereby forming a MTJ stack.

摘要翻译： 提供半导体器件和制造方法，例如MTJ器件和制造MTJ器件的方法。 MTJ装置可以包括底部电极，MTJ堆叠和顶部电极，其中顶部电极使用填充孔技术形成。 顶部电极可以具有倾斜的侧壁。 可以通过沉积相应的MTJ层来形成MTJ堆叠。 可以在MTJ层上形成并图案化图案化掩模以形成限定顶部电极的开口。 开口填充有导电材料以形成顶部电极。 然后将顶部电极用作掩模以对MTJ层进行图案化，从而形成MTJ堆叠。

公开(公告)号：US20130043549A1

公开(公告)日：2013-02-21

申请号：US13618908

申请日：2012-09-14

申请人： Wei-Hang Huang ,  Shih-Chang Liu ,  Chern-Yow Hsu ,  Fu-Ting Sung ,  Chia-Shiung Tsai

发明人： Wei-Hang Huang ,  Shih-Chang Liu ,  Chern-Yow Hsu ,  Fu-Ting Sung ,  Chia-Shiung Tsai

IPC分类号： H01L29/82

CPC分类号： H01L43/12 ,  G11C11/16

摘要： A semiconductor device and a method of manufacture are provided, such as a MTJ device and a method of manufacturing a MTJ device. The MTJ device may include a bottom electrode, a MTJ stack, and a top electrode, wherein the top electrode is formed using a hole-filling technique. The top electrode may have slanted sidewalls. The MTJ stack may be formed by depositing corresponding MTJ layers. A patterned mask may be formed and patterned over the MTJ layers to form an opening defining the top electrode. The opening is filled with a conductive material to form the top electrode. The top electrode is then used as a mask to pattern the MTJ layers, thereby forming a MTJ stack.

摘要翻译： 提供半导体器件和制造方法，例如MTJ器件和制造MTJ器件的方法。 MTJ装置可以包括底部电极，MTJ堆叠和顶部电极，其中顶部电极使用填充孔技术形成。 顶部电极可以具有倾斜的侧壁。 可以通过沉积相应的MTJ层来形成MTJ堆叠。 可以在MTJ层上形成并图案化图案化掩模以形成限定顶部电极的开口。 开口填充有导电材料以形成顶部电极。 然后将顶部电极用作掩模以对MTJ层进行图案化，从而形成MTJ堆叠。

公开(公告)号：US08313959B1

公开(公告)日：2012-11-20

申请号：US13211909

申请日：2011-08-17

申请人： Wei-Hang Huang ,  Shih-Chang Liu ,  Chern-Yow Hsu ,  Fu-Ting Sung ,  Chia-Shiung Tsai

发明人： Wei-Hang Huang ,  Shih-Chang Liu ,  Chern-Yow Hsu ,  Fu-Ting Sung ,  Chia-Shiung Tsai

IPC分类号： H01L21/00

CPC分类号： H01L43/12 ,  G11C11/16

摘要： A semiconductor device and a method of manufacture are provided, such as a MTJ device and a method of manufacturing a MTJ device. The MTJ device may include a bottom electrode, a MTJ stack, and a top electrode, wherein the top electrode is formed using a hole-filling technique. The top electrode may have slanted sidewalls. The MTJ stack may be formed by depositing corresponding MTJ layers. A patterned mask may be formed and patterned over the MTJ layers to form an opening defining the top electrode. The opening is filled with a conductive material to form the top electrode. The top electrode is then used as a mask to pattern the MTJ layers, thereby forming a MTJ stack.

摘要翻译： 提供半导体器件和制造方法，例如MTJ器件和制造MTJ器件的方法。 MTJ装置可以包括底部电极，MTJ堆叠和顶部电极，其中顶部电极使用填充孔技术形成。 顶部电极可以具有倾斜的侧壁。 可以通过沉积相应的MTJ层来形成MTJ堆叠。 可以在MTJ层上形成并图案化图案化掩模以形成限定顶部电极的开口。 开口填充有导电材料以形成顶部电极。 然后将顶部电极用作掩模以对MTJ层进行图案化，从而形成MTJ堆叠。

公开(公告)号：US10553785B2

公开(公告)日：2020-02-04

申请号：US13452230

申请日：2012-04-20

申请人： Chern-Yow Hsu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

发明人： Chern-Yow Hsu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC分类号： H01L27/22 ,  H01L43/08 ,  H01L43/12 ,  G11C11/16

摘要： This description relates to a method for fabricating a magnetoresistive random access memory (MRAM) device having a plurality of magnetic tunnel junction (MTJ) units. The method includes forming a bottom conductive layer, forming an anti-ferromagnetic layer and forming a tunnel layer over the bottom conductive layer and the anti-ferromagnetic layer. The method further includes forming a free magnetic layer, having a magnetic moment aligned in a direction that is adjustable by applying an electromagnetic field, over the tunnel layer and forming a top conductive layer over the free magnetic layer. The method further includes performing at least one lithographic process to remove portions of the bottom conductive layer, the anti-ferromagnetic layer, the tunnel layer, the free magnetic layer and the top conductive layer that is uncovered by the photoresist layer until the bottom conductive layer is exposed and removing portions of at least one sidewall of the MTJ unit.

公开(公告)号：US20130026585A1

公开(公告)日：2013-01-31

申请号：US13190966

申请日：2011-07-26

申请人： Fu-Ting Sung ,  Shih-Chang Liu ,  Chia-Shiung Tsai

发明人： Fu-Ting Sung ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC分类号： H01L29/82 ,  H01L43/12

CPC分类号： H01L43/12 ,  H01L43/08

摘要： According to an embodiment, a magnetoresistive random access memory (MRAM) device comprises a bottom electrode, a stack, a dielectric material, a dielectric layer, and a conductive material. The bottom electrode is over a substrate, and the stack is over the bottom electrode. The stack comprises a magnetic tunnel junction (MTJ) and a top electrode. The dielectric material is along a sidewall of the stack, and the dielectric material has a height greater than a thickness of the MTJ and less than a stack height. The dielectric layer is over the stack and the dielectric material. The conductive material extends through the dielectric layer to the top electrode of the stack.

公开(公告)号：US08921959B2

公开(公告)日：2014-12-30

申请号：US13190966

申请日：2011-07-26

申请人： Fu-Ting Sung ,  Shih-Chang Liu ,  Chia-Shiung Tsai

发明人： Fu-Ting Sung ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC分类号： H01L29/82 ,  G11C11/00 ,  H01L21/00 ,  H01L43/12 ,  H01L43/08

CPC分类号： H01L43/12 ,  H01L43/08

摘要： According to an embodiment, a magnetoresistive random access memory (MRAM) device comprises a bottom electrode, a stack, a dielectric material, a dielectric layer, and a conductive material. The bottom electrode is over a substrate, and the stack is over the bottom electrode. The stack comprises a magnetic tunnel junction (MTJ) and a top electrode. The dielectric material is along a sidewall of the stack, and the dielectric material has a height greater than a thickness of the MTJ and less than a stack height. The dielectric layer is over the stack and the dielectric material. The conductive material extends through the dielectric layer to the top electrode of the stack.

摘要翻译： 根据实施例，磁阻随机存取存储器（MRAM）器件包括底部电极，堆叠，电介质材料，电介质层和导电材料。 底部电极在衬底上方，并且堆叠层在底部电极之上。 堆叠包括磁性隧道结（MTJ）和顶部电极。 介电材料沿着堆叠的侧壁，并且电介质材料具有高于MTJ的厚度并小于堆叠高度的高度。 电介质层在电池堆和电介质材料之上。 导电材料通过电介质层延伸到堆叠的顶部电极。

公开(公告)号：US08889507B2

公开(公告)日：2014-11-18

申请号：US11765971

申请日：2007-06-20

申请人： Chih-Ta Wu ,  Jason Lee ,  Chung Chien Wang ,  Hsing-Lien Lin ,  Yu-Jen Wang ,  Yeur-Luen Tu ,  Chern-Yow Hsu ,  Yuan-Hung Liu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Lucy Chang ,  Chia-Lin Chen ,  Ming-Chih Tsai

发明人： Chih-Ta Wu ,  Jason Lee ,  Chung Chien Wang ,  Hsing-Lien Lin ,  Yu-Jen Wang ,  Yeur-Luen Tu ,  Chern-Yow Hsu ,  Yuan-Hung Liu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Lucy Chang ,  Chia-Lin Chen ,  Ming-Chih Tsai

IPC分类号： H01L21/8234 ,  H01L21/8244 ,  H01L49/02 ,  H01L27/108

CPC分类号： H01L27/10814 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/75

摘要： A capacitor and methods for forming the same are provided. The method includes forming a bottom electrode; treating the bottom electrode in an oxygen-containing environment to convert a top layer of the bottom electrode into a buffer layer; forming an insulating layer on the buffer layer; and forming a top electrode over the insulating layer.

摘要翻译： 提供电容器及其形成方法。 该方法包括形成底部电极; 在含氧环境中处理底部电极以将底部电极的顶层转化为缓冲层; 在缓冲层上形成绝缘层; 并在所述绝缘层上形成顶部电极。

公开(公告)号：US20080318378A1

公开(公告)日：2008-12-25

申请号：US11765971

申请日：2007-06-20

申请人： Chih-Ta Wu ,  Jason Lee ,  Chung Chien Wang ,  Hsing-Lien Lin ,  Yu-Jen Wang ,  Yeur-Luen Tu ,  Chern-Yow Hsu ,  Yuan-Hung Liu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Lucy Chang ,  Chia-Lin Chen ,  Ming-Chih Tsai

发明人： Chih-Ta Wu ,  Jason Lee ,  Chung Chien Wang ,  Hsing-Lien Lin ,  Yu-Jen Wang ,  Yeur-Luen Tu ,  Chern-Yow Hsu ,  Yuan-Hung Liu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Lucy Chang ,  Chia-Lin Chen ,  Ming-Chih Tsai

IPC分类号： H01L21/20 ,  H01L21/8242

CPC分类号： H01L27/10814 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/75

摘要： A capacitor and methods for forming the same are provided. The method includes forming a bottom electrode; treating the bottom electrode in an oxygen-containing environment to convert a top layer of the bottom electrode into a buffer layer; forming an insulating layer on the buffer layer; and forming a top electrode over the insulating layer.

摘要翻译： 提供电容器及其形成方法。 该方法包括形成底部电极; 在含氧环境中处理底部电极以将底部电极的顶层转化为缓冲层; 在缓冲层上形成绝缘层; 并在所述绝缘层上形成顶部电极。

公开(公告)号：US08629531B2

公开(公告)日：2014-01-14

申请号：US13030645

申请日：2011-02-18

申请人： Ming Chyi Liu ,  Hsieh Ching Pei ,  Jiun-Lei Yu ,  Chi-Ming Chen ,  Shih-Chang Liu ,  Chung-Yi Yu ,  Chia-Shiung Tsai

发明人： Ming Chyi Liu ,  Hsieh Ching Pei ,  Jiun-Lei Yu ,  Chi-Ming Chen ,  Shih-Chang Liu ,  Chung-Yi Yu ,  Chia-Shiung Tsai

IPC分类号： H01L21/20 ,  H01L21/18

CPC分类号： H01L29/7787 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/0649 ,  H01L29/107 ,  H01L29/2003 ,  H01L29/66462 ,  H01L33/007 ,  H01L33/12

摘要： The present disclosure provides a semiconductor structure. The semiconductor structure includes a dielectric material layer on a silicon substrate, the dielectric material layer being patterned to define a plurality of regions separated by the dielectric material layer; a first buffer layer disposed on the silicon substrate; a heterogeneous buffer layer disposed on the first buffer layer; and a gallium nitride layer grown on the heterogeneous buffer layer only within the plurality of regions.

摘要翻译： 本公开提供了一种半导体结构。 所述半导体结构包括在硅衬底上的电介质材料层，所述电介质材料层被构图以限定由所述电介质材料层分隔的多个区域; 设置在所述硅衬底上的第一缓冲层; 设置在所述第一缓冲层上的异质缓冲层; 以及仅在多个区域内在异质缓冲层上生长的氮化镓层。

公开(公告)号：US20120211759A1

公开(公告)日：2012-08-23

申请号：US13030645

申请日：2011-02-18

申请人： Ming Chyi Liu ,  Hsieh Ching Pei ,  Jiun-Lei Yu ,  Chi-Ming Chen ,  Shih-Chang Liu ,  Chung-Yi Yu ,  Chia-Shiung Tsai

发明人： Ming Chyi Liu ,  Hsieh Ching Pei ,  Jiun-Lei Yu ,  Chi-Ming Chen ,  Shih-Chang Liu ,  Chung-Yi Yu ,  Chia-Shiung Tsai

IPC分类号： H01L29/20 ,  H01L21/20

CPC分类号： H01L29/7787 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/0649 ,  H01L29/107 ,  H01L29/2003 ,  H01L29/66462 ,  H01L33/007 ,  H01L33/12

摘要： The present disclosure provides a semiconductor structure. The semiconductor structure includes a dielectric material layer on a silicon substrate, the dielectric material layer being patterned to define a plurality of regions separated by the dielectric material layer; a first buffer layer disposed on the silicon substrate; a heterogeneous buffer layer disposed on the first buffer layer; and a gallium nitride layer grown on the heterogeneous buffer layer only within the plurality of regions.

摘要翻译： 本公开提供了一种半导体结构。 所述半导体结构包括在硅衬底上的电介质材料层，所述电介质材料层被构图以限定由所述电介质材料层分隔的多个区域; 设置在所述硅衬底上的第一缓冲层; 设置在所述第一缓冲层上的异质缓冲层; 以及仅在多个区域内在异质缓冲层上生长的氮化镓层。