公开(公告)号：US08786310B1

公开(公告)日：2014-07-22

申请号：US13588647

申请日：2012-08-17

申请人： Weiguang Lu ,  Paige A. Kolze ,  William W. Stiehl ,  Robert M. Balzli, Jr. ,  Carl M. Stern ,  Chen W. Tseng

发明人： Weiguang Lu ,  Paige A. Kolze ,  William W. Stiehl ,  Robert M. Balzli, Jr. ,  Carl M. Stern ,  Chen W. Tseng

IPC分类号： H01L25/00 ,  H03K19/173 ,  G06F7/38 ,  G06F17/50

CPC分类号： G06F7/38 ,  G06F17/5027 ,  H01L25/00 ,  H01L2924/0002 ,  H03K19/173 ,  H03K19/17756 ,  H03K19/1776 ,  H01L2924/00

摘要： Approaches for partially reconfiguring a frame are disclosed. In one approach, a circuit arrangement includes programmable resources, frames of configuration memory cells, and partial configuration control memory cells. Each frame includes a plurality of subsets of configuration memory cells, and each subset configures one of the programmable resources. Each partial configuration control memory cell is coupled to a respective one of the subsets. Responsive to a first partial bitstream that includes a quantity of configuration data for all the subsets of configuration cells of a first frame of the plurality of frames, each subset of the configuration memory cells of the first frame is configurable or not configurable responsive to the state of the associated partial configuration control memory cell.

摘要翻译： 公开了部分重新配置帧的方法。 在一种方法中，电路装置包括可编程资源，配置存储单元的帧和部分配置控制存储单元。 每个帧包括配置存储器单元的多个子集，并且每个子集配置可编程资源之一。 每个部分配置控制存储器单元耦合到相应的一个子集。 响应于第一部分比特流，其包括多个帧的第一帧的配置单元的所有子集的配置数据量，第一帧的配置存储器单元的每个子集可配置或不可配置，以响应于状态 的相关部分配置控制存储单元。

公开(公告)号：US08633730B1

公开(公告)日：2014-01-21

申请号：US13588435

申请日：2012-08-17

申请人： Chen W. Tseng ,  Weiguang Lu ,  William W. Stiehl ,  Robert M. Balzli, Jr. ,  Carl M. Stern ,  Aditya Chaubal ,  Derrick S. Woods

发明人： Chen W. Tseng ,  Weiguang Lu ,  William W. Stiehl ,  Robert M. Balzli, Jr. ,  Carl M. Stern ,  Aditya Chaubal ,  Derrick S. Woods

IPC分类号： H03K19/173 ,  H03K19/177 ,  G06F1/24 ,  G06F17/50

CPC分类号： H03K19/17768 ,  G06F1/24 ,  G06F1/3287 ,  H03K19/17708 ,  Y02D10/171 ,  Y02D50/20

摘要： When a first sub-circuit of a programmable integrated circuit (“IC”) is to be deactivated, a global write enable (GWE) signal is deasserted. In response to deassertion of the GWE signal and a first memory cell associated with the first sub-circuit being in a first state, flip-flops in the first sub-circuit are disabled from changing state. In response to memory cells associated with sub-circuits other than the first sub-circuit being in a second state, flip-flops in the other sub-circuits are enabled to change state. When the first sub-circuit is to be activated, the GWE signal is asserted. Logic implemented by the first sub-circuit is preserved between the deasserting and the asserting of the GWE signal. In response to assertion of the GWE signal and the first memory cell associated with the first sub-circuit being in the first state, flip-flops in the first sub-circuit are enabled to change state.

摘要翻译： 当可编程集成电路（“IC”）的第一子电路要被去激活时，全局写使能（GWE）信号被断言。 响应于GWE信号的取消取消和与第一子电路处于第一状态相关联的第一存储单元，第一子电路中的触发器被禁止改变状态。 响应于与第一子电路以外的子电路相关联的存储器单元处于第二状态，其他子电路中的触发器能够改变状态。 当第一个子电路被激活时，GWE信号被断言。 由第一子电路实现的逻辑在GWE信号的解除和断言之间得以保留。 响应于GWE信号的断言和与第一子电路处于第一状态相关联的第一存储单元，第一子电路中的触发器能够改变状态。

公开(公告)号：US08713409B1

公开(公告)日：2014-04-29

申请号：US13525922

申请日：2012-06-18

申请人： Chen W. Tseng ,  Weiguang Lu ,  Christopher Y. Karman

发明人： Chen W. Tseng ,  Weiguang Lu ,  Christopher Y. Karman

IPC分类号： G11C29/00

CPC分类号： G11C29/52 ,  G11C5/005 ,  G11C11/4125 ,  G11C2029/0409

摘要： Approaches for mitigating single event upsets (SEUs) in a circuit arrangement. In response to each bit error of a plurality of bit errors, an error address indicative of the bit error in a configuration memory cell in the circuit arrangement is translated into a non-volatile memory address. A partial bitstream at the non-volatile memory address is read from a non-volatile memory. Successive partial bitstreams read in response to successive ones of the bit errors are alternately transmitted to first and second internal configuration ports. A subset of configuration memory cells of the circuit arrangement, including the configuration memory cell referenced by the error address, is reconfigured with the partial bitstream.

摘要翻译： 减轻电路安排中的单事件扰乱（SEU）的方法。 响应于多个比特错误的每个比特错误，指示电路布置中的配置存储单元中的比特错误的错误地址被转换为非易失性存储器地址。 从非易失性存储器读取非易失性存储器地址处的部分比特流。 响应于连续的位错误而读取的连续的部分比特流被交替地发送到第一和第二内部配置端口。 包括由错误地址引用的配置存储器单元的电路装置的配置存储器单元的子集与部分位流重新配置。

公开(公告)号：US07990173B1

公开(公告)日：2011-08-02

申请号：US12725324

申请日：2010-03-16

申请人： Chen W. Tseng ,  Carl H. Carmichael

发明人： Chen W. Tseng ,  Carl H. Carmichael

IPC分类号： H03K19/003 ,  H03K19/007

CPC分类号： H03K19/0033 ,  H03K19/17764

摘要： A circuit for handling single event upsets includes a plurality of digital clock manager circuits. A plurality of counters are respectively coupled by their inputs to the outputs of the digital clock managers and a reset controller is coupled to the outputs of the counters. The reset controller is configured to determine an expected value of the counters. In response to an output value of one of the counters being less than the expected value, the reset controller triggers a reset of the digital clock manager coupled to the input of the one of the counters. In response to an output value of one of the counters being greater than or equal to the expected value, the reset controller continues operation without triggering a reset of a digital clock manager.

摘要翻译： 用于处理单事件故障的电路包括多个数字时钟管理器电路。 多个计数器分别通过它们的输入耦合到数字时钟管理器的输出，并且复位控制器耦合到计数器的输出端。 复位控制器被配置为确定计数器的期望值。 响应于其中一个计数器的输出值小于期望值，复位控制器触发耦合到一个计数器的输入端的数字时钟管理器的复位。 响应于其中一个计数器的输出值大于或等于预期值，复位控制器继续操作而不触发数字时钟管理器的复位。