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    Partially programming an integrated circuit using control memory cells
    1.
    发明授权
    Partially programming an integrated circuit using control memory cells 有权
    使用控制存储单元对集成电路进行部分编程

    公开(公告)号：US08786310B1

    公开(公告)日：2014-07-22

    申请号：US13588647

    申请日：2012-08-17

    申请人： Weiguang Lu ,  Paige A. Kolze ,  William W. Stiehl ,  Robert M. Balzli, Jr. ,  Carl M. Stern ,  Chen W. Tseng

    发明人： Weiguang Lu ,  Paige A. Kolze ,  William W. Stiehl ,  Robert M. Balzli, Jr. ,  Carl M. Stern ,  Chen W. Tseng

    IPC分类号： H01L25/00 ,  H03K19/173 ,  G06F7/38 ,  G06F17/50

    CPC分类号： G06F7/38 ,  G06F17/5027 ,  H01L25/00 ,  H01L2924/0002 ,  H03K19/173 ,  H03K19/17756 ,  H03K19/1776 ,  H01L2924/00

    摘要： Approaches for partially reconfiguring a frame are disclosed. In one approach, a circuit arrangement includes programmable resources, frames of configuration memory cells, and partial configuration control memory cells. Each frame includes a plurality of subsets of configuration memory cells, and each subset configures one of the programmable resources. Each partial configuration control memory cell is coupled to a respective one of the subsets. Responsive to a first partial bitstream that includes a quantity of configuration data for all the subsets of configuration cells of a first frame of the plurality of frames, each subset of the configuration memory cells of the first frame is configurable or not configurable responsive to the state of the associated partial configuration control memory cell.

    摘要翻译： 公开了部分重新配置帧的方法。 在一种方法中，电路装置包括可编程资源，配置存储单元的帧和部分配置控制存储单元。 每个帧包括配置存储器单元的多个子集，并且每个子集配置可编程资源之一。 每个部分配置控制存储器单元耦合到相应的一个子集。 响应于第一部分比特流，其包括多个帧的第一帧的配置单元的所有子集的配置数据量，第一帧的配置存储器单元的每个子集可配置或不可配置，以响应于状态 的相关部分配置控制存储单元。

    Power control using global control signal to selected circuitry in a programmable integrated circuit
    2.
    发明授权
    Power control using global control signal to selected circuitry in a programmable integrated circuit 有权
    使用全局控制信号对可编程集成电路中的选定电路进行功率控制

    公开(公告)号：US08633730B1

    公开(公告)日：2014-01-21

    申请号：US13588435

    申请日：2012-08-17

    申请人： Chen W. Tseng ,  Weiguang Lu ,  William W. Stiehl ,  Robert M. Balzli, Jr. ,  Carl M. Stern ,  Aditya Chaubal ,  Derrick S. Woods

    发明人： Chen W. Tseng ,  Weiguang Lu ,  William W. Stiehl ,  Robert M. Balzli, Jr. ,  Carl M. Stern ,  Aditya Chaubal ,  Derrick S. Woods

    IPC分类号： H03K19/173 ,  H03K19/177 ,  G06F1/24 ,  G06F17/50

    CPC分类号： H03K19/17768 ,  G06F1/24 ,  G06F1/3287 ,  H03K19/17708 ,  Y02D10/171 ,  Y02D50/20

    摘要： When a first sub-circuit of a programmable integrated circuit (“IC”) is to be deactivated, a global write enable (GWE) signal is deasserted. In response to deassertion of the GWE signal and a first memory cell associated with the first sub-circuit being in a first state, flip-flops in the first sub-circuit are disabled from changing state. In response to memory cells associated with sub-circuits other than the first sub-circuit being in a second state, flip-flops in the other sub-circuits are enabled to change state. When the first sub-circuit is to be activated, the GWE signal is asserted. Logic implemented by the first sub-circuit is preserved between the deasserting and the asserting of the GWE signal. In response to assertion of the GWE signal and the first memory cell associated with the first sub-circuit being in the first state, flip-flops in the first sub-circuit are enabled to change state.

    摘要翻译： 当可编程集成电路（“IC”）的第一子电路要被去激活时，全局写使能（GWE）信号被断言。 响应于GWE信号的取消取消和与第一子电路处于第一状态相关联的第一存储单元，第一子电路中的触发器被禁止改变状态。 响应于与第一子电路以外的子电路相关联的存储器单元处于第二状态，其他子电路中的触发器能够改变状态。 当第一个子电路被激活时，GWE信号被断言。 由第一子电路实现的逻辑在GWE信号的解除和断言之间得以保留。 响应于GWE信号的断言和与第一子电路处于第一状态相关联的第一存储单元，第一子电路中的触发器能够改变状态。

    Bit error mitigation
    3.
    发明授权
    Bit error mitigation 有权
    位错误缓解

    公开(公告)号：US08713409B1

    公开(公告)日：2014-04-29

    申请号：US13525922

    申请日：2012-06-18

    申请人： Chen W. Tseng ,  Weiguang Lu ,  Christopher Y. Karman

    发明人： Chen W. Tseng ,  Weiguang Lu ,  Christopher Y. Karman

    IPC分类号： G11C29/00

    CPC分类号： G11C29/52 ,  G11C5/005 ,  G11C11/4125 ,  G11C2029/0409

    摘要： Approaches for mitigating single event upsets (SEUs) in a circuit arrangement. In response to each bit error of a plurality of bit errors, an error address indicative of the bit error in a configuration memory cell in the circuit arrangement is translated into a non-volatile memory address. A partial bitstream at the non-volatile memory address is read from a non-volatile memory. Successive partial bitstreams read in response to successive ones of the bit errors are alternately transmitted to first and second internal configuration ports. A subset of configuration memory cells of the circuit arrangement, including the configuration memory cell referenced by the error address, is reconfigured with the partial bitstream.

    摘要翻译： 减轻电路安排中的单事件扰乱（SEU）的方法。 响应于多个比特错误的每个比特错误，指示电路布置中的配置存储单元中的比特错误的错误地址被转换为非易失性存储器地址。 从非易失性存储器读取非易失性存储器地址处的部分比特流。 响应于连续的位错误而读取的连续的部分比特流被交替地发送到第一和第二内部配置端口。 包括由错误地址引用的配置存储器单元的电路装置的配置存储器单元的子集与部分位流重新配置。

    Self-checking and self-correcting internal configuration port circuitry
    4.
    发明授权
    Self-checking and self-correcting internal configuration port circuitry 有权
    自检和自校正内部配置端口电路

    公开(公告)号：US08099625B1

    公开(公告)日：2012-01-17

    申请号：US12418522

    申请日：2009-04-03

    申请人： Chen Wei Tseng ,  Weiguang Lu ,  Matthew P. Baker

    发明人： Chen Wei Tseng ,  Weiguang Lu ,  Matthew P. Baker

    IPC分类号： G06F11/00 ,  G06F11/16

    CPC分类号： G06F11/142 ,  G06F11/2017

    摘要： Method and apparatus for self-checking and self-correcting memory states of a programmable resource is described. Programmable resource of an integrated circuit has a first core and a second core instantiated therein. A first internal configuration port and a second internal configuration port of the integrated circuit are respectively connected to the first core and the second core. The second core is coupled to the first core for monitoring operation of the first core with the second core, and the second core is configured to obtain control responsive to a failure of the first core or the first internal configuration port for a self-correcting mode.

    摘要翻译： 描述了可编程资源的自检和自校正存储器状态的方法和装置。 集成电路的可编程资源具有在其中实例化的第一核心和第二核心。 集成电路的第一内部配置端口和第二内部配置端口分别连接到第一核心和第二核心。 第二核心耦合到第一核心，用于监视具有第二核心的第一核心的操作，并且第二核心被配置为获得响应于第一核心或第一内部配置端口的故障的控制以进行自校正模式 。

    Mitigating the effect of single event transients on input/output pins of an integrated circuit device
    5.
    发明授权
    Mitigating the effect of single event transients on input/output pins of an integrated circuit device 有权
    减轻单个事件瞬变对集成电路设备的输入/输出引脚的影响

    公开(公告)号：US08384418B1

    公开(公告)日：2013-02-26

    申请号：US13071453

    申请日：2011-03-24

    申请人： Weiguang Lu ,  Matthew P. Baker

    发明人： Weiguang Lu ,  Matthew P. Baker

    IPC分类号： H03K19/003 ,  H03K19/007

    CPC分类号： H03K19/003 ,  H03K19/007

    摘要： A system for protecting an input/output (I/O) pin of an integrated circuit device (IC) from single event transients is disclosed. The system includes a first delay circuit that is configured to delay a clock signal from the clock source by a first predetermined amount of time, and a second delay circuit that is configured to delay the clock signal by a second predetermined amount of time. The system further includes a first register that is clocked by the clock signal, a second register that is clocked by the clock signal delayed by the first predetermined amount of time, and a third register that is clocked by the clock signal delayed by the second predetermined amount of time. The system also includes voter circuits, where each voter circuit is configured to receive a first data signal from an output of the first register, a second data signal from an output of the second register, and a third data signal from an output of the third register.

    摘要翻译： 公开了一种用于保护集成电路器件（IC）的输入/输出（I / O）引脚免受单事件瞬变的系统。 该系统包括：第一延迟电路，被配置为将来自时钟源的时钟信号延迟第一预定时间量;以及第二延迟电路，其被配置为将时钟信号延迟第二预定时间量。 该系统还包括由时钟信号定时的第一寄存器，由延迟了第一预定时间量的时钟信号计时的第二寄存器，以及由延迟了第二预定时间的时钟信号计时的第三寄存器 多少时间。 该系统还包括选民电路，其中每个选举电路被配置为从第一寄存器的输出接收第一数据信号，从第二寄存器的输出接收第二数据信号，并从第三数据信号输出第三数据信号 寄存器。

    Secure design-for-test scan chains
    6.
    发明授权
    Secure design-for-test scan chains 有权
    安全的测试扫描链

    公开(公告)号：US08438436B1

    公开(公告)日：2013-05-07

    申请号：US12794221

    申请日：2010-06-04

    申请人： Matthew P. Baker ,  Weiguang Lu

    发明人： Matthew P. Baker ,  Weiguang Lu

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318588

    摘要： A method of securing a design-for-test scan chain within a programmable integrated circuit device (IC) can include placing the programmable IC in an operational mode and responsive to a request to access a scan chain within the programmable IC, selectively enabling a secure mode within the programmable IC according to a configuration state of the programmable IC. Enabling secure mode within the programmable IC can provide access to the scan chain. Responsive to enabling the secure mode, the programmable IC can remain in the secure mode and be prevented from re-entering the operational mode until the programmable IC is power cycled.

    摘要翻译： 将可设计的测试扫描链固定在可编程集成电路设备（IC）内的方法可以包括将可编程IC放置在操作模式中并且响应于访问可编程IC内的扫描链的请求，选择性地实现安全 根据可编程IC的配置状态在可编程IC内的模式。 在可编程IC中启用安全模式可以提供对扫描链的访问。 响应于启用安全模式，可编程IC可以保持在安全模式并且被阻止重新进入操作模式，直到可编程IC被电力循环。

    Circuit for and method of repairing defective memory
    7.
    发明授权
    Circuit for and method of repairing defective memory 有权
    电路和修复缺陷记忆的方法

    公开(公告)号：US08103919B1

    公开(公告)日：2012-01-24

    申请号：US12359212

    申请日：2009-01-23

    申请人： Subodh Kumar ,  Weiguang Lu

    发明人： Subodh Kumar ,  Weiguang Lu

    IPC分类号： G11C29/00 ,  G01R31/28

    CPC分类号： G11C29/785 ,  G11C2029/4402

    摘要： A circuit for repairing defective memory of an integrated circuit is disclosed. The circuit includes blocks of memory; and interconnect elements providing data to each of the blocks of memory, where the interconnect elements enable coupling together the signals for programming the blocks of memory. The circuit also includes a directory of locations for defective memory cells of blocks of memory, where the directory of locations is common to the blocks of memory for storing locations of defective memory cells of the blocks of memory. Methods of repairing defective memory of an integrated circuit are also disclosed.

    摘要翻译： 公开了一种用于修复集成电路的有缺陷的存储器的电路。 该电路包括存储器块; 以及向每个存储器块提供数据的互连元件，其中互连元件使得能够将信号耦合在一起以对存储器块进行编程。 该电路还包括存储器块的缺陷存储器单元的位置目录，其中位置目录对于用于存储存储器块的缺陷存储器单元的位置的存储器块是共同的。 还公开了修复集成电路的有缺陷的存储器的方法。