公开(公告)号：US20050121794A1

公开(公告)日：2005-06-09

申请号：US11026822

申请日：2004-12-29

申请人： Werner Juengling ,  Kirk Prall ,  Ravi Iyer ,  Gurtej Sandhu ,  Guy Blalock

发明人： Werner Juengling ,  Kirk Prall ,  Ravi Iyer ,  Gurtej Sandhu ,  Guy Blalock

IPC分类号： H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/40

CPC分类号： H01L23/5222 ,  H01L21/02115 ,  H01L21/02118 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/02362 ,  H01L21/31695 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention encompasses methods of forming insulating materials between conductive elements. In one aspect, the invention includes a method of forming a material adjacent a conductive electrical component comprising: a) partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within it. In another aspect, the invention includes a method of forming a material between a pair of conductive electrical components comprising the following steps: a) forming a pair of conductive electrical components within a mass and separated by an expanse of the mass; b) forming at least one support member within the expanse of the mass, the support member not comprising a conductive interconnect; and c) vaporizing the expanse of the mass to a degree effective to form at least one void between the support member and each of the pair of conductive electrical components. In another aspect, the invention includes an insulating material adjacent a conductive electrical component, the insulating material comprising a matrix and at least one void within the matrix. In another aspect, the invention includes an insulating region between a pair of conductive electrical components comprising: a) a support member between the conductive electrical components, the support member not comprising a conductive interconnect; and b) at least one void between the support member and each of the pair of conductive electrical components.

摘要翻译： 本发明包括在导电元件之间形成绝缘材料的方法。 在一个方面，本发明包括形成邻近导电电气部件的材料的方法，该方法包括：a）部分蒸发物质以形成邻近导电电气部件的基体，所述基质在其内具有至少一个空隙。 另一方面，本发明包括一种在一对导电电气部件之间形成材料的方法，包括以下步骤：a）在质量体内形成一对导电的电气部件，并由质量块的一部分分隔; b）在所述物体的宽度内形成至少一个支撑构件，所述支撑构件不包括导电互连; 以及c）将所述物质的所述膨胀物蒸发至有效地在所述支撑构件和所述一对导电电气部件中的每一个之间形成至少一个空隙的程度。 在另一方面，本发明包括与导电电气部件相邻的绝缘材料，所述绝缘材料包含基体和所述基体内的至少一个空隙。 在另一方面，本发明包括在一对导电电气部件之间的绝缘区域，包括：a）导电电气部件之间的支撑部件，所述支撑部件不包括导电互连; 以及b）所述支撑构件和所述一对导电电气部件中的每一个之间的至少一个空隙。

公开(公告)号：US07115509B2

公开(公告)日：2006-10-03

申请号：US10714752

申请日：2003-11-17

申请人： Chun Chen ,  Guy Blalock ,  Graham Wolstenholme ,  Kirk Prall

发明人： Chun Chen ,  Guy Blalock ,  Graham Wolstenholme ,  Kirk Prall

IPC分类号： H01L21/44

CPC分类号： H01L27/11521 ,  H01L21/76895 ,  H01L27/115

摘要： Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, allowing the deposition and etching of polysilicon local interconnects to source regions of array transistors. By providing for a local interconnect of polysilicon, a smaller source region and/or drain region can also be utilized, further decreasing the required word line spacing. Low resistance polysilicon local source interconnects can also couple to an increased number of memory cells, thereby reducing the number of contacts made to an array ground.

摘要翻译： 描述了方法和装置以便于形成具有低电阻多晶硅局部互连的存储器件，其允许更小的阵列特征尺寸，并因此促进形成更密集阵列格式的阵列。 使用具有高选择性的湿蚀刻工艺形成本发明的实施例，允许将多晶硅局部互连件沉积和蚀刻到阵列晶体管的源极区域。 通过提供多晶硅的局部互连，还可以利用更小的源极区和/或漏极区，进一步减少所需的字线间隔。 低电阻多晶硅本地源极互连还可以耦合到增加数量的存储器单元，从而减少对阵列地阵进行的触点的数量。

公开(公告)号：US20050285148A1

公开(公告)日：2005-12-29

申请号：US11217739

申请日：2005-09-01

申请人： Chun Chen ,  Guy Blalock ,  Graham Wolstenholme ,  Kirk Prall

发明人： Chun Chen ,  Guy Blalock ,  Graham Wolstenholme ,  Kirk Prall

IPC分类号： H01L21/336 ,  H01L21/768 ,  H01L21/8247 ,  H01L23/48 ,  H01L27/115 ,  H01L29/76 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/76895 ,  H01L27/115

摘要： Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, allowing the deposition and etching of polysilicon local interconnects to source regions of array transistors. By providing for a local interconnect of polysilicon, a smaller source region and/or drain region can also be utilized, further decreasing the required word line spacing. Low resistance polysilicon local source interconnects can also couple to an increased number of memory cells, thereby reducing the number of contacts made to an array ground.

摘要翻译： 描述了方法和装置以便于形成具有低电阻多晶硅局部互连的存储器件，其允许更小的阵列特征尺寸，并因此促进形成更密集阵列格式的阵列。 使用具有高选择性的湿蚀刻工艺形成本发明的实施例，允许将多晶硅局部互连件沉积和蚀刻到阵列晶体管的源极区域。 通过提供多晶硅的局部互连，还可以利用更小的源极区和/或漏极区，进一步减少所需的字线间隔。 低电阻多晶硅本地源极互连还可以耦合到增加数量的存储器单元，从而减少对阵列地阵进行的触点的数量。

公开(公告)号：US6080675A

公开(公告)日：2000-06-27

申请号：US344435

申请日：1999-06-25

申请人： Kirk Prall ,  Guy Blalock

发明人： Kirk Prall ,  Guy Blalock

IPC分类号： H01L21/306 ,  H01L21/311 ,  H01L21/3213

CPC分类号： H01L21/02043 ,  Y02P80/30 ,  Y10S438/906 ,  Y10S438/928

摘要： A method for manufacturing a semiconductor device on a wafer that has a substrate with a front side and a backside, and an accumulation of waste matter on the backside of the substrate. In a method of the invention, a covet layer is deposited over the front side in a normal coating step of a process for fabricating a component on the wafer. The cover layer provides material used in the process for fabricating the component on the front side of the wafer and creates a barrier over the front side. The waste matter is removed from the backside of the wafer by etching the waste matter from the backside of the wafer with a suitable etchant, or by planarizing the backside of the wafer with a chemical-mechanical planarization ("CMP") process. During the removal step, the cover layer protects the front side and any device features on the front side from being damaged while the waste matter is removed from the backside of the wafer. Since the cover layer is deposited in a normal coating step of the process for fabricating a component on the wafer, it is deposited irrespective of whether the waste matter is removed from the wafer.

摘要翻译： 一种在晶片上制造半导体器件的方法，该半导体器件具有正面和背面的衬底，以及在衬底的背面积聚废物。 在本发明的方法中，在用于制造晶片上的部件的工艺的正常涂覆步骤中，在前侧上沉积蜂窝层。 覆盖层提供用于制造晶片正面上的部件的工艺中使用的材料，并在前侧形成阻挡层。 通过用合适的蚀刻剂从晶片的背面蚀刻废物，或者通过化学机械平坦化（“CMP”）工艺平坦化晶片的背面，从晶片的背面去除废物。 在去除步骤期间，覆盖层保护前侧，并且当废物从晶片的背面移除时，前侧上的任何装置特征不被损坏。 由于覆盖层在用于制造晶片上的部件的工艺的正常涂覆步骤中沉积，所以不管废物是否从晶片上移除，都被沉积。

公开(公告)号：US5958796A

公开(公告)日：1999-09-28

申请号：US915193

申请日：1997-08-20

申请人： Kirk Prall ,  Guy Blalock

发明人： Kirk Prall ,  Guy Blalock

IPC分类号： H01L21/306 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/28 ,  H01L21/31 ,  H01L21/3205

CPC分类号： H01L21/02043 ,  Y02P80/30 ,  Y10S438/906 ,  Y10S438/928

摘要： A method for manufacturing a semiconductor device on a wafer that has a substrate with a front side and a backside, and an accumulation of waste matter on the backside of the substrate. In a method of the invention, a cover layer is deposited over the front side in a normal coating step of a process for fabricating a component on the wafer. The cover layer provides material used in the process for fabricating the component on the front side of the wafer and creates a barrier over the front side. The waste matter is removed from the backside of the wafer by etching the waste matter from the backside of the wafer with a suitable etchant, or by planarizing the backside of the wafer with a chemical-mechanical planarization ("CMP") process. During the removal step, the cover layer protects the front side and any device features on the front side from being damaged while the waste matter is removed from the backside of the wafer. Since the cover layer is deposited in a normal coating step of the process for fabricating a component on the wafer, it is deposited irrespective of whether the waste matter is removed from the wafer.

摘要翻译： 一种在晶片上制造半导体器件的方法，该半导体器件具有正面和背面的衬底，以及在衬底的背面积聚废物。 在本发明的方法中，在用于在晶片上制造部件的工艺的正常涂覆步骤中，在正面上沉积覆盖层。 覆盖层提供用于制造晶片正面上的部件的工艺中使用的材料，并在前侧形成阻挡层。 通过用合适的蚀刻剂从晶片的背面蚀刻废物，或者通过化学机械平坦化（“CMP”）工艺平坦化晶片的背面，从晶片的背面去除废物。 在去除步骤期间，覆盖层保护前侧，并且当废物从晶片的背面移除时，前侧上的任何装置特征不被损坏。 由于覆盖层在用于制造晶片上的部件的工艺的正常涂覆步骤中沉积，所以不管废物是否从晶片上移除，都被沉积。

公开(公告)号：US5858865A

公开(公告)日：1999-01-12

申请号：US569838

申请日：1995-12-07

申请人： Werner Juengling ,  Kirk Prall ,  Gordon Haller ,  David Keller ,  Tyler Lowrey

发明人： Werner Juengling ,  Kirk Prall ,  Gordon Haller ,  David Keller ,  Tyler Lowrey

IPC分类号： H01L21/28 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/485 ,  H01L21/3205

CPC分类号： H01L27/10888 ,  H01L21/28 ,  H01L21/768 ,  H01L21/76897 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S438/978

摘要： Within an integrated circuit, a contact plug with a height not extending above the level of the gate/wordline nitride is nonetheless provided with a relatively large contact area or landing pad, significantly larger than the source/drain region to which the contact plug is electrically connected. Methods for producing the inventive contact plug include (1) use of a nitride facet etch, either (a) during a nitride spacer formation etch or (b) during a BPSG etch; (2) using at least one of (a) an isotropic photoresist etch or partial descum to narrow BPSG spacers above the gate/wordline nitride, and (b) a nitride step etch to etch the shoulder area of the gate/wordline nitride exposed by a BPSG etch; and (3) polishing a BPSG layer down to the top of a gate/wordline nitride before any doped polysilicon plug fill, masking for BPSG etch and performing a BPSG etch, etching the photoresist layer through a partial descum, and etching the shoulder area of the gate/wordline nitride exposed thereby.

摘要翻译： 在集成电路中，具有不延伸在栅极/字线氮化物的高度之上的高度的接触插塞仍然设置有相对较大的接触面积或着陆焊盘，其明显大于接触插塞电接触的源极/漏极区域 连接的。 用于制造本发明接触塞的方法包括（1）在氮化物间隔物形成蚀刻期间使用氮化物刻面蚀刻（a）或（b）在BPSG蚀刻期间; （2）使用（a）各向同性光致抗蚀剂蚀刻或部分除去中的至少一种来窄化栅极/字线氮化物之上的BPSG间隔区，以及（b）氮化物步骤蚀刻以蚀刻暴露于栅极/字线氮化物的肩部区域 BPSG蚀刻; 并且（3）在任何掺杂的多晶硅插塞填充之前将BPSG层向下抛光到栅极/字线氮化物的顶部，掩蔽用于BPSG蚀刻和执行BPSG蚀刻，通过部分除去蚀刻光致抗蚀剂层，并蚀刻 栅极/字线氮化物被曝光。

公开(公告)号：US20060009035A1

公开(公告)日：2006-01-12

申请号：US11218099

申请日：2005-09-01

申请人： Chun Chen ,  Guy Blalock ,  Graham Wolstenholme ,  Kirk Prall

发明人： Chun Chen ,  Guy Blalock ,  Graham Wolstenholme ,  Kirk Prall

IPC分类号： H01L21/44

CPC分类号： H01L27/11521 ,  H01L21/76895 ,  H01L27/115

摘要： Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, allowing the deposition and etching of polysilicon local interconnects to source regions of array transistors. By providing for a local interconnect of polysilicon, a smaller source region and/or drain region can also be utilized, further decreasing the required word line spacing. Low resistance polysilicon local source interconnects can also couple to an increased number of memory cells, thereby reducing the number of contacts made to an array ground.

公开(公告)号：US20060008989A1

公开(公告)日：2006-01-12

申请号：US11217946

申请日：2005-09-01

申请人： Chun Chen ,  Guy Blalock ,  Graham Wolstenholme ,  Kirk Prall

发明人： Chun Chen ,  Guy Blalock ,  Graham Wolstenholme ,  Kirk Prall

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/76895 ,  H01L27/115

摘要： Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, allowing the deposition and etching of polysilicon local interconnects to source regions of array transistors. By providing for a local interconnect of polysilicon, a smaller source region and/or drain region can also be utilized, further decreasing the required word line spacing. Low resistance polysilicon local source interconnects can also couple to an increased number of memory cells, thereby reducing the number of contacts made to an array ground.

公开(公告)号：US06448656B1

公开(公告)日：2002-09-10

申请号：US09583679

申请日：2000-05-31

申请人： Fernando Gonzalez ,  Guy Blalock ,  Kirk Prall

发明人： Fernando Gonzalez ,  Guy Blalock ,  Kirk Prall

IPC分类号： H01L2348

CPC分类号： H01L23/5283 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a connection is comprised of the steps of depositing a lower conductor. A dielectric layer is deposited on the lower conductor, with the dielectric layer having a lower surface adjacent to the lower conductor, and having an upper surface. An opening extending between the upper surface and the lower surface of the dielectric layer is formed. A conductive plug is deposited within the opening, with the plug having an upper surface proximate the upper surface of the dielectric layer. The upper surface has an edge where the upper surface of the plug is adjacent to the dielectric layer. A recess is formed proximate to the edge of the upper surface of the plug, the recess extending into both the plug and the dielectric layer. Finally, an upper conductor is deposited on the upper surface of the dielectric layer and the upper surface of the plug. A connection thus formed is also disclosed.

摘要翻译： 形成连接的方法包括沉积下导体的步骤。 电介质层沉积在下导体上，电介质层具有与下导体相邻的下表面，并具有上表面。 形成在电介质层的上表面和下表面之间延伸的开口。 导电插塞沉积在开口内，插头具有接近电介质层的上表面的上表面。 上表面具有插头的上表面与电介质层相邻的边缘。 在插头的上表面的边缘附近形成凹部，凹部延伸到插塞和介电层两者中。 最后，在电介质层的上表面和插头的上表面上沉积上导体。 还公开了如此形成的连接。

公开(公告)号：US5892285A

公开(公告)日：1999-04-06

申请号：US801345

申请日：1997-02-19

申请人： Fernando Gonzalez ,  Guy Blalock ,  Kirk Prall

发明人： Fernando Gonzalez ,  Guy Blalock ,  Kirk Prall

IPC分类号： H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L23/5283 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/535 ,  H01L2924/0002

摘要： A method of forming a connection is comprised of the steps of depositing a lower conductor. A dielectric layer is deposited on the lower conductor, with the dielectric layer having a lower surface adjacent to the lower conductor, and having an upper surface. An opening extending between the upper surface and the lower surface of the dielectric layer is formed. A conductive plug is deposited within the opening, with the plug having an upper surface proximate the upper surface of the dielectric layer. The upper surface has an edge where the upper surface of the plug is adjacent to the dielectric layer. A recess is formed proximate to the edge of the upper surface of the plug, the recess extending into both the plug and the dielectric layer. Finally, an upper conductor is deposited on the upper surface of the dielectric layer and the upper surface of the plug. A connection thus formed is also disclosed.

摘要翻译： 形成连接的方法包括沉积下导体的步骤。 电介质层沉积在下导体上，电介质层具有与下导体相邻的下表面，并具有上表面。 形成在电介质层的上表面和下表面之间延伸的开口。 导电插塞沉积在开口内，插头具有接近电介质层的上表面的上表面。 上表面具有插头的上表面与电介质层相邻的边缘。 在插头的上表面的边缘附近形成凹部，凹部延伸到插塞和介电层两者中。 最后，在电介质层的上表面和插头的上表面上沉积上导体。 还公开了如此形成的连接。