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173 条记录 (耗时 0.035 秒)

    Fusible link in an integrated semiconductor circuit and process for producing the fusible link
    1.
    发明授权
    Fusible link in an integrated semiconductor circuit and process for producing the fusible link 失效
    集成半导体电路中的可熔链路和用于生产可熔链路的工艺

    公开(公告)号：US6080649A

    公开(公告)日：2000-06-27

    申请号：US780492

    申请日：1997-01-08

    申请人： Wolfgang Werner ,  Karlheinz Muller ,  Holger Pohle

    发明人： Wolfgang Werner ,  Karlheinz Muller ,  Holger Pohle

    IPC分类号： H01L21/82 ,  H01L23/525 ,  H01L23/58 ,  H01L21/44

    CPC分类号： H01L23/5256 ,  H01L2924/0002

    摘要： A fusible link in an integrated semiconductor circuit and a process for producing the fusible link contemplate the disposition of a fusible link, which is constructed with a cross-sectional constriction as a desired fusing point for its conductor track, in a void. A surface of the void and/or a bare conductor track can be covered with a protection layer, to prevent corrosion. The advantages of such a fusible link are a lower ignition energy and increased reliability. The fusible link may be used as a memory element of a PROM.

    摘要翻译： 集成半导体电路中的可熔链路和用于制造可熔连接的工艺的过程考虑到在空隙中构造有作为其导体轨迹的期望的熔合点的横截面收缩的可熔连接件的布置。 空隙和/或裸导体轨道的表面可以用保护层覆盖，以防止腐蚀。 这种可熔连接件的优点是较低的点火能量和更高的可靠性。 可熔链路可以用作PROM的存储元件。

    Semiconductor component with dielectric layer stack and voltage divider
    2.
    发明授权
    Semiconductor component with dielectric layer stack and voltage divider 有权

    公开(公告)号：US09786659B2

    公开(公告)日：2017-10-10

    申请号：US12862821

    申请日：2010-08-25

    申请人： Wolfgang Werner

    发明人： Wolfgang Werner

    IPC分类号： H01L27/088 ,  H01L23/52 ,  H01L27/08 ,  H01L27/06

    CPC分类号： H01L27/0802 ,  H01L23/52 ,  H01L27/0676 ,  H01L27/0805 ,  H01L27/0814

    摘要： A semiconductor component has a semiconductor body zone, a first electrically conductive layer adjacent to the semiconductor body zone, a first dielectric layer with first dielectric properties and a second dielectric layer with second dielectric properties. The first dielectric properties differ from the second dielectric properties. The first dielectric layer and the second dielectric layer are arranged between the semiconductor body zone and the first electrically conductive layer. A second electrically conductive layer is applied between the first dielectric layer and the second dielectric layer. A first voltage divider is switched between the first electrically conductive layer and the semiconductor body zone. The second electrically conductive layer is electrically conductively connected only to the voltage divider.

    Fuse in chip design
    3.
    发明授权
    Fuse in chip design 有权
    保险丝芯片设计

    公开(公告)号：US09368308B2

    公开(公告)日：2016-06-14

    申请号：US11571787

    申请日：2005-06-27

    申请人： Werner Blum ,  Reiner Friedrich ,  Reimer Hinrichs ,  Wolfgang Werner

    发明人： Werner Blum ,  Reiner Friedrich ,  Reimer Hinrichs ,  Wolfgang Werner

    IPC分类号： H01H85/04 ,  H01H69/02 ,  H01H85/00 ,  H01H85/046 ,  H01H85/041

    CPC分类号： H01H85/046 ,  H01H69/022 ,  H01H85/006 ,  H01H85/0411 ,  H01H2085/0414 ,  Y10T29/49107

    摘要： In order to produce a cost-effective fuse in chip design, which is applied to a carrier substrate made of a Al2O3 ceramic having a high thermal conductivity, and which is provided with a fusible metallic conductor and a cover layer, in which the melting point of the metallic conductor may be defined reliably, it is suggested that an intermediate layer having low thermal conductivity be positioned between the carrier substrate and the metallic conductor, the intermediate layer being formed by a low-melting-point inorganic glass paste applied in the screen-printing method or an organic intermediate layer applied in island printing. Furthermore, a method for manufacturing the fuse is specified.

    摘要翻译： 为了生产具有成本效益的芯片设计保险丝，其应用于由具有高导热性的Al 2 O 3陶瓷制成的载体衬底，并且具有可熔金属导体和覆盖层，其中熔点 可以可靠地限定金属导体，建议在载体基板和金属导体之间设置导热性低的中间层，中间层由施加在屏幕上的低熔点无机玻璃浆料形成 印刷方法或在岛印刷中应用的有机中间层。 此外，规定了制造保险丝的方法。

    Normally-off semiconductor switches and normally-off JFETs
    4.
    发明授权
    Normally-off semiconductor switches and normally-off JFETs 有权
    常关半导体开关和常闭JFET

    公开(公告)号：US09343588B2

    公开(公告)日：2016-05-17

    申请号：US13031956

    申请日：2011-02-22

    申请人： Wolfgang Werner

    发明人： Wolfgang Werner

    IPC分类号： H01L29/808 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423

    CPC分类号： H01L29/808 ,  H01L29/1066 ,  H01L29/41758 ,  H01L29/42316 ,  H01L29/8083

    摘要： A normally-off JFET is provided. The normally-off JFET includes a channel region of a first conductivity type, a floating semiconductor region of a second conductivity type adjoining the channel region, and a contact region of the first conductivity type adjoining the floating semiconductor region. The floating semiconductor region is arranged between the contact region and the channel region. Further, a normally-off semiconductor switch is provided.

    摘要翻译： 提供常闭JFET。 常关的JFET包括第一导电类型的沟道区，与沟道区邻接的第二导电类型的浮动半导体区以及与浮置半导体区邻接的第一导电类型的接触区。 浮置半导体区域布置在接触区域和沟道区域之间。 此外，提供常闭半导体开关。

    Vertical trench transistor
    10.
    发明授权
    Vertical trench transistor 有权
    垂直沟槽晶体管

    公开(公告)号：US07511336B2

    公开(公告)日：2009-03-31

    申请号：US11287154

    申请日：2005-11-25

    申请人： Franz Hirler ,  Wolfgang Werner ,  Joachim Krumery

    发明人： Franz Hirler ,  Wolfgang Werner ,  Joachim Krumery

    IPC分类号： H01L29/94

    CPC分类号： H01L29/7813 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/7806

    摘要： A vertical trench transistor has a first electrode, a second electrode and also a semiconductor body arranged between the first and second electrodes, there being formed in the semiconductor body a plurality of transistor cells comprising source region, body region, drift region and gate electrode and also contact holes for making contact with the source and body regions, contact being made with the source and body regions by means of the first electrode, and at least the bottom of each contact hole adjoining at least one drift region, so that Schottky contacts between the first electrode and corresponding drift regions are formed at the bottoms of the contact holes. The dimensions and configurations of the body regions or of the body contact regions optionally arranged between body regions and contact holes are chosen in such a way as to avoid excessive increases in electric fields at the edges of the contact hole bottoms.

    摘要翻译： 垂直沟槽晶体管具有第一电极，第二电极和布置在第一和第二电极之间的半导体本体，在半导体本体中形成多个晶体管单元，其包括源极区域，体区域，漂移区域和栅极电极，以及 还接触用于与源区和主体区接触的孔，借助于第一电极与源极和主体区进行接触，并且至少每个接触孔的底部与至少一个漂移区相邻，使得肖特基接触在 第一电极和相应的漂移区形成在接触孔的底部。 选择布置在主体区域和接触孔之间的身体区域或身体接触区域的尺寸和结构被选择为避免接触孔底部边缘处的电场过度增加。