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173 条记录 (耗时 0.035 秒)

    Ink jet print head
    1.
    发明授权
    Ink jet print head 失效
    喷墨打印头

    公开(公告)号：US6099106A

    公开(公告)日：2000-08-08

    申请号：US52346

    申请日：1998-03-30

    申请人： Wolfgang Werner ,  Thomas Zettler

    发明人： Wolfgang Werner ,  Thomas Zettler

    IPC分类号： B41J2/045 ,  B41J2/055 ,  B41J2/14 ,  B41J2/16 ,  B41J2/01

    CPC分类号： B41J2/1646 ,  B41J2/14 ,  B41J2/14072 ,  B41J2/14129 ,  B41J2/14201 ,  B41J2/1603 ,  B41J2/1607 ,  B41J2/1623 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1631 ,  B41J2/1632 ,  B41J2/1642 ,  B41J2202/13 ,  Y10S29/016 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49401

    摘要： The ink jet print head is formed with many parallel ducts, which are etched isotropically through openings in a first layer located above the ducts. After the etching operation, the openings of the first layer are closed by the deposition onto the first layer of a second layer, which covers the openings. The openings have a diameter of 1 .mu.m, for instance. The openings, formed in the first layer by photolithography and ensuing dry etching, are disposed such that in an etching operation, the desired ducts underneath the first layer are laid bare. It is thus not necessary to adjust the relative positioning of two or more etched plates, closed ducts are formed without bonding or adhesive techniques, and the trigger circuit and the print head can be integrated on a single substrate.

    摘要翻译： 喷墨打印头形成有许多平行的管道，其通过位于管道上方的第一层中的开口各向同性地蚀刻。 在蚀刻操作之后，通过沉积到覆盖开口的第二层的第一层上来封闭第一层的开口。 例如，开口的直径为1μm。 通过光刻和随后的干蚀刻在第一层中形成的开口被布置成使得在蚀刻操作中，将第一层下方的期望的导管铺设成裸露。 因此，不需要调整两个或更多个蚀刻板的相对定位，在没有结合或粘合技术的情况下形成封闭的管道，并且触发电路和打印头可以集成在单个基板上。

    Ink jet print head and method of producing the ink print head
    2.
    发明授权
    Ink jet print head and method of producing the ink print head 失效
    喷墨打印头和墨水打印头的制造方法

    公开(公告)号：US06397467B1

    公开(公告)日：2002-06-04

    申请号：US09528417

    申请日：2000-03-17

    申请人： Wolfgang Werner ,  Thomas Zettler

    发明人： Wolfgang Werner ,  Thomas Zettler

    IPC分类号： B21D5376

    CPC分类号： B41J2/1646 ,  B41J2/14 ,  B41J2/14072 ,  B41J2/14129 ,  B41J2/14201 ,  B41J2/1603 ,  B41J2/1607 ,  B41J2/1623 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1631 ,  B41J2/1632 ,  B41J2/1642 ,  B41J2202/13 ,  Y10S29/016 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49401

    摘要： The ink jet print head is formed with many parallel ducts, which are etched isotropically through openings in a first layer located above the ducts. After the etching operation, the openings of the first layer are closed by the deposition onto the first layer of a second layer, which covers the openings. The openings have a diameter of 1 &mgr;m, for instance. The openings, formed in the first layer by photolithography and ensuing dry etching, are disposed such that in an etching operation, the desired ducts underneath the first layer are laid bare. It is thus not necessary to adjust the relative positioning of two or more etched plates, closed ducts are formed without bonding or adhesive techniques, and the trigger circuit and the print head can be integrated on a single substrate.

    摘要翻译： 喷墨打印头形成有许多平行的管道，其通过位于管道上方的第一层中的开口各向同性地蚀刻。 在蚀刻操作之后，通过沉积到覆盖开口的第二层的第一层上来封闭第一层的开口。 例如，开口的直径为1um。 通过光刻和随后的干蚀刻在第一层中形成的开口被布置成使得在蚀刻操作中，将第一层下方的期望的导管铺设成裸露。 因此，不需要调整两个或更多个蚀刻板的相对定位，在没有结合或粘合技术的情况下形成封闭的管道，并且触发电路和打印头可以集成在单个基板上。

    Semiconductor component with dielectric layer stack and voltage divider
    3.
    发明授权
    Semiconductor component with dielectric layer stack and voltage divider 有权

    公开(公告)号：US09786659B2

    公开(公告)日：2017-10-10

    申请号：US12862821

    申请日：2010-08-25

    申请人： Wolfgang Werner

    发明人： Wolfgang Werner

    IPC分类号： H01L27/088 ,  H01L23/52 ,  H01L27/08 ,  H01L27/06

    CPC分类号： H01L27/0802 ,  H01L23/52 ,  H01L27/0676 ,  H01L27/0805 ,  H01L27/0814

    摘要： A semiconductor component has a semiconductor body zone, a first electrically conductive layer adjacent to the semiconductor body zone, a first dielectric layer with first dielectric properties and a second dielectric layer with second dielectric properties. The first dielectric properties differ from the second dielectric properties. The first dielectric layer and the second dielectric layer are arranged between the semiconductor body zone and the first electrically conductive layer. A second electrically conductive layer is applied between the first dielectric layer and the second dielectric layer. A first voltage divider is switched between the first electrically conductive layer and the semiconductor body zone. The second electrically conductive layer is electrically conductively connected only to the voltage divider.

    Fuse in chip design
    4.
    发明授权
    Fuse in chip design 有权
    保险丝芯片设计

    公开(公告)号：US09368308B2

    公开(公告)日：2016-06-14

    申请号：US11571787

    申请日：2005-06-27

    申请人： Werner Blum ,  Reiner Friedrich ,  Reimer Hinrichs ,  Wolfgang Werner

    发明人： Werner Blum ,  Reiner Friedrich ,  Reimer Hinrichs ,  Wolfgang Werner

    IPC分类号： H01H85/04 ,  H01H69/02 ,  H01H85/00 ,  H01H85/046 ,  H01H85/041

    CPC分类号： H01H85/046 ,  H01H69/022 ,  H01H85/006 ,  H01H85/0411 ,  H01H2085/0414 ,  Y10T29/49107

    摘要： In order to produce a cost-effective fuse in chip design, which is applied to a carrier substrate made of a Al2O3 ceramic having a high thermal conductivity, and which is provided with a fusible metallic conductor and a cover layer, in which the melting point of the metallic conductor may be defined reliably, it is suggested that an intermediate layer having low thermal conductivity be positioned between the carrier substrate and the metallic conductor, the intermediate layer being formed by a low-melting-point inorganic glass paste applied in the screen-printing method or an organic intermediate layer applied in island printing. Furthermore, a method for manufacturing the fuse is specified.

    摘要翻译： 为了生产具有成本效益的芯片设计保险丝，其应用于由具有高导热性的Al 2 O 3陶瓷制成的载体衬底，并且具有可熔金属导体和覆盖层，其中熔点 可以可靠地限定金属导体，建议在载体基板和金属导体之间设置导热性低的中间层，中间层由施加在屏幕上的低熔点无机玻璃浆料形成 印刷方法或在岛印刷中应用的有机中间层。 此外，规定了制造保险丝的方法。

    Normally-off semiconductor switches and normally-off JFETs
    5.
    发明授权
    Normally-off semiconductor switches and normally-off JFETs 有权
    常关半导体开关和常闭JFET

    公开(公告)号：US09343588B2

    公开(公告)日：2016-05-17

    申请号：US13031956

    申请日：2011-02-22

    申请人： Wolfgang Werner

    发明人： Wolfgang Werner

    IPC分类号： H01L29/808 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423

    CPC分类号： H01L29/808 ,  H01L29/1066 ,  H01L29/41758 ,  H01L29/42316 ,  H01L29/8083

    摘要： A normally-off JFET is provided. The normally-off JFET includes a channel region of a first conductivity type, a floating semiconductor region of a second conductivity type adjoining the channel region, and a contact region of the first conductivity type adjoining the floating semiconductor region. The floating semiconductor region is arranged between the contact region and the channel region. Further, a normally-off semiconductor switch is provided.

    摘要翻译： 提供常闭JFET。 常关的JFET包括第一导电类型的沟道区，与沟道区邻接的第二导电类型的浮动半导体区以及与浮置半导体区邻接的第一导电类型的接触区。 浮置半导体区域布置在接触区域和沟道区域之间。 此外，提供常闭半导体开关。