Methods for fabricating improved gate dielectrics
    1.
    发明授权
    Methods for fabricating improved gate dielectrics 有权
    制造改进的栅极电介质的方法

    公开(公告)号:US07879737B2

    公开(公告)日:2011-02-01

    申请号:US12801115

    申请日:2010-05-24

    IPC分类号: H01L21/31

    摘要: Disclosed are a variety of methods for increasing the relative thickness in the peripheral or edge regions of gate dielectric patterns to suppress leakage through these regions. The methods provide alternatives to conventional GPOX processes and provide the improved leakage resistance without incurring the degree of increased gate electrode resistance associated with GPOX processes. Each of the methods includes forming a first opening to expose an active area region, forming an oxidation control region on the exposed portion and then forming a second opening whereby a peripheral region free of the oxidation control region is exposed for formation of a gate dielectric layer. The resulting gate dielectric layers are characterized by a thinner central region surrounded or bounded by a thicker peripheral region.

    摘要翻译: 公开了用于增加栅极电介质图案的外围或边缘区域中的相对厚度以抑制这些区域的泄漏的各种方法。 这些方法提供了常规GPOX工艺的替代方案,并提供改进的耐漏电性,而不会导致与GPOX工艺相关的增加的栅电极电阻的程度。 每种方法包括形成第一开口以暴露有源区域区域,在暴露部分上形成氧化控制区域,然后形成第二开口,由此暴露氧化控制区域的外围区域以形成栅极介电层 。 得到的栅极介电层的特征在于由较厚的外围区域包围或界定的较薄的中心区域。

    Methods for fabricating improved gate dielectrics
    2.
    发明授权
    Methods for fabricating improved gate dielectrics 失效
    制造改进的栅极电介质的方法

    公开(公告)号:US07759263B2

    公开(公告)日:2010-07-20

    申请号:US11806338

    申请日:2007-05-31

    IPC分类号: H01L21/336

    摘要: Disclosed are a variety of methods for increasing the relative thickness in the peripheral or edge regions of gate dielectric patterns to suppress leakage through these regions. The methods provide alternatives to conventional GPOX processes and provide the improved leakage resistance without incurring the degree of increased gate electrode resistance associated with GPOX processes. Each of the methods includes forming a first opening to expose an active area region, forming an oxidation control region on the exposed portion and then forming a second opening whereby a peripheral region free of the oxidation control region is exposed for formation of a gate dielectric layer. The resulting gate dielectric layers are characterized by a thinner central region surrounded or bounded by a thicker peripheral region.

    摘要翻译: 公开了用于增加栅极电介质图案的外围或边缘区域中的相对厚度以抑制这些区域的泄漏的各种方法。 这些方法提供了常规GPOX工艺的替代方案,并提供改进的耐漏电性,而不会导致与GPOX工艺相关的增加的栅电极电阻的程度。 每种方法包括形成第一开口以暴露有源区域区域,在暴露部分上形成氧化控制区域,然后形成第二开口,由此暴露氧化控制区域的外围区域以形成栅极介电层 。 得到的栅极介电层的特征在于由较厚的外围区域包围或界定的较薄的中心区域。

    Methods for fabricating improved gate dielectrics
    3.
    发明申请
    Methods for fabricating improved gate dielectrics 失效
    制造改进的栅极电介质的方法

    公开(公告)号:US20080014700A1

    公开(公告)日:2008-01-17

    申请号:US11806338

    申请日:2007-05-31

    IPC分类号: H01L21/336

    摘要: Disclosed are a variety of methods for increasing the relative thickness in the peripheral or edge regions of gate dielectric patterns to suppress leakage through these regions. The methods provide alternatives to conventional GPOX processes and provide the improved leakage resistance without incurring the degree of increased gate electrode resistance associated with GPOX processes. Each of the methods includes forming a first opening to expose an active area region, forming an oxidation control region on the exposed portion and then forming a second opening whereby a peripheral region free of the oxidation control region is exposed for formation of a gate dielectric layer. The resulting gate dielectric layers are characterized by a thinner central region surrounded or bounded by a thicker peripheral region.

    摘要翻译: 公开了用于增加栅极电介质图案的外围或边缘区域中的相对厚度以抑制这些区域的泄漏的各种方法。 这些方法提供了常规GPOX工艺的替代方案,并提供改进的耐漏电性,而不会导致与GPOX工艺相关的增加的栅电极电阻的程度。 每种方法包括形成第一开口以暴露有源区域区域,在暴露部分上形成氧化控制区域,然后形成第二开口,由此暴露氧化控制区域的外围区域以形成栅极介电层 。 得到的栅极介电层的特征在于由较厚的外围区域包围或界定的较薄的中心区域。

    Method of forming semiconductor device
    4.
    发明授权
    Method of forming semiconductor device 有权
    半导体器件形成方法

    公开(公告)号:US07550353B2

    公开(公告)日:2009-06-23

    申请号:US11685644

    申请日:2007-03-13

    IPC分类号: H01L21/8236

    摘要: One embodiment of a method for forming a semiconductor device can include forming a gate pattern on a semiconductor substrate and performing a selective re-oxidation process on the gate pattern in gas ambient including hydrogen, oxygen, and nitrogen. When the gate pattern includes a tunnel insulation layer, a metal nitride layer and a metal layer, the selective re-oxidation process heals the etching damage of a gate pattern and simultaneously prevents oxidation of the metal nitride layer and a tungsten electrode.

    摘要翻译: 用于形成半导体器件的方法的一个实施例可以包括在半导体衬底上形成栅极图案,并且在包括氢,氧和氮在内的气体环境中对栅极图案进行选择性再氧化处理。 当栅极图案包括隧道绝缘层,金属氮化物层和金属层时,选择性再氧化工艺会修复栅极图案的蚀刻损伤,同时防止金属氮化物层和钨电极的氧化。

    Nonvolatile memory device and method for forming the same
    7.
    发明申请
    Nonvolatile memory device and method for forming the same 审中-公开
    非易失存储器件及其形成方法

    公开(公告)号:US20080093663A1

    公开(公告)日:2008-04-24

    申请号:US11882654

    申请日:2007-08-03

    IPC分类号: H01L21/336 H01L29/792

    摘要: A method of forming a memory device includes forming a first insulating pattern and a polysilicon pattern in a peripheral region of a substrate, forming a cell gate insulating pattern including a second insulating pattern, a charge storage pattern, and a third insulating pattern in a cell region of the substrate, forming a barrier metal layer on the polysilicon pattern and on the third insulating pattern, forming a conductive layer on the barrier metal layer, patterning the conductive layer to simultaneously form a first conductive pattern on the polysilicon pattern and a second conductive pattern on the third insulating pattern, and patterning the barrier metal layer to simultaneously form a first barrier metal pattern on the polysilicon pattern and a second barrier metal pattern on the third insulating pattern.

    摘要翻译: 形成存储器件的方法包括在衬底的周边区域中形成第一绝缘图案和多晶硅图案,在单元中形成包括第二绝缘图案,电荷存储图案和第三绝缘图案的单元栅极绝缘图案 在所述多晶硅图案和所述第三绝缘图案上形成阻挡金属层,在所述阻挡金属层上形成导电层,图案化所述导电层以同时在所述多晶硅图案上形成第一导电图案,并且将第二导电 图案化所述阻挡金属层,同时在所述多晶硅图案上形成第一阻挡金属图案,以及在所述第三绝缘图案上形成第二阻挡金属图案。

    Semiconductor memory device and method of manufacturing the same
    8.
    发明授权
    Semiconductor memory device and method of manufacturing the same 有权
    半导体存储器件及其制造方法

    公开(公告)号:US07585787B2

    公开(公告)日:2009-09-08

    申请号:US11648595

    申请日:2007-01-03

    IPC分类号: H01L21/469

    摘要: A semiconductor memory device, e.g., a charge trapping type non-volatile memory device, may include a charge trapping structure formed in a first area of a substrate and a gate structure formed in a second area of the substrate. The charge trapping structure may include a tunnel oxide layer pattern, a charge trapping layer pattern and a dielectric layer pattern of aluminum-containing tertiary metal oxide. The gate structure may include a gate oxide layer pattern, a polysilicon layer pattern and an ohmic layer pattern of aluminum-containing tertiary metal silicide. A first electrode and a second electrode may be formed on the charge trapping structure. A lower electrode and an upper electrode may be provided on the gate structure. The dielectric layer pattern may have a higher dielectric constant, and the ohmic layer pattern may have improved thermal stability, thereby enhancing programming and erasing operations of the charge trapping type non-volatile memory device.

    摘要翻译: 半导体存储器件,例如电荷俘获型非易失性存储器件,可以包括形成在衬底的第一区域中的电荷俘获结构和形成在衬底的第二区域中的栅极结构。 电荷捕获结构可以包括隧道氧化物层图案,电荷俘获层图案和含铝三级金属氧化物的介电层图案。 栅极结构可以包括栅极氧化物层图案,多晶硅层图案和含铝三次金属硅化物的欧姆层图案。 第一电极和第二电极可以形成在电荷捕获结构上。 可以在栅极结构上设置下电极和上电极。 电介质层图案可以具有更高的介电常数,并且欧姆层图案可以具有改善的热稳定性,从而增强电荷俘获型非易失性存储器件的编程和擦除操作。

    Semiconductor memory device and method of manufacturing the same
    10.
    发明申请
    Semiconductor memory device and method of manufacturing the same 有权
    半导体存储器件及其制造方法

    公开(公告)号:US20080079056A1

    公开(公告)日:2008-04-03

    申请号:US11648595

    申请日:2007-01-03

    IPC分类号: H01L29/76

    摘要: A semiconductor memory device, e.g., a charge trapping type non-volatile memory device, may include a charge trapping structure formed in a first area of a substrate and a gate structure formed in a second area of the substrate. The charge trapping structure may include a tunnel oxide layer pattern, a charge trapping layer pattern and a dielectric layer pattern of aluminum-containing tertiary metal oxide. The gate structure may include a gate oxide layer pattern, a polysilicon layer pattern and an ohmic layer pattern of aluminum-containing tertiary metal silicide. A first electrode and a second electrode may be formed on the charge trapping structure. A lower electrode and an upper electrode may be provided on the gate structure. The dielectric layer pattern may have a higher dielectric constant, and the ohmic layer pattern may have improved thermal stability, thereby enhancing programming and erasing operations of the charge trapping type non-volatile memory device.

    摘要翻译: 半导体存储器件,例如电荷俘获型非易失性存储器件,可以包括形成在衬底的第一区域中的电荷俘获结构和形成在衬底的第二区域中的栅极结构。 电荷捕获结构可以包括隧道氧化物层图案,电荷俘获层图案和含铝三级金属氧化物的介电层图案。 栅极结构可以包括栅极氧化物层图案,多晶硅层图案和含铝三次金属硅化物的欧姆层图案。 第一电极和第二电极可以形成在电荷捕获结构上。 可以在栅极结构上设置下电极和上电极。 电介质层图案可以具有更高的介电常数,并且欧姆层图案可以具有改善的热稳定性,从而增强电荷俘获型非易失性存储器件的编程和擦除操作。