公开(公告)号：US20160307779A1

公开(公告)日：2016-10-20

申请号：US15098278

申请日：2016-04-13

Applicant: XINTEC INC.

Inventor： Yu-Tung CHEN ,  Quan-Qun SU ,  Chuan-Jin SHIU ,  Chien-Hui CHEN ,  Hsiao-Lan YEH ,  Yen-Shih HO

IPC: H01L21/56 ,  H01L21/67 ,  B05B1/24 ,  H01L21/78 ,  H01L23/29 ,  H01L23/00 ,  H01L21/687 ,  H01L21/768

CPC classification number: H01L21/561 ,  H01L21/02118 ,  H01L21/02282 ,  H01L21/6715 ,  H01L21/68742 ,  H01L21/68764 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/11 ,  H01L24/94 ,  H01L2224/02313 ,  H01L2224/0346 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/014

Abstract: A wafer coating system includes a wafer chuck, a flowing insulating material sprayer and a wafer tilting lifting pin. The wafer chuck has a carrier part and a rotating part, which the carrier part is mounted on the rotating part to carry a wafer, and the rotating part is configured to rotate with a predetermined axis. The flowing insulating material sprayer is above the wafer chuck and configured to spray a flowing insulating material to the wafer, and the wafer tilting lifting pin is configured to form a first acute angle between the wafer and direction of gravity.

Abstract translation: 晶片涂布系统包括晶片卡盘，流动绝缘材料喷雾器和晶片倾斜提升销。 晶片卡盘具有托架部和旋转部，托架部安装在旋转部上以承载晶片，旋转部构造成以预定轴旋转。 流动的绝缘材料喷雾器位于晶片卡盘之上，并配置成将流动的绝缘材料喷射到晶片上，并且晶片倾斜提升销构造成在晶片和重心之间形成第一锐角。

公开(公告)号：US20160329283A1

公开(公告)日：2016-11-10

申请号：US15140289

申请日：2016-04-27

Applicant: XINTEC INC.

Inventor： Yu-Tung CHEN ,  Chien-Min LIN ,  Chuan-Jin SHIU ,  Chih-Wei HO ,  Yen-Shih HO

IPC: H01L23/528 ,  H01L23/00 ,  H01L21/768 ,  H01L21/027 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/0271 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0345 ,  H01L2224/0557

Abstract: A semiconductor structure includes a first substrate, a second substrate, a dam layer, a photoresist layer, and a conductive layer. The first substrate has a conductive pad. The second substrate has a through via, a sidewall surface surrounding the through via, a first surface, and a second surface opposite to the first surface. The through via penetrates through the first and second surfaces. The conductive pad is aligned with the through via. The dam layer is located between the first substrate and the second surface. The dam layer protrudes toward the through via. The photoresist layer is located on the first surface, the sidewall surface, the dam layer protruding toward the through via, and between the conductive pad and the dam layer protruding toward the through via. The conductive layer is located on the photoresist layer and the conductive pad.

Abstract translation: 半导体结构包括第一基板，第二基板，阻挡层，光致抗蚀剂层和导电层。 第一基板具有导电垫。 第二基板具有通孔，围绕通孔的侧壁表面，第一表面和与第一表面相对的第二表面。 通孔穿过第一和第二表面。 导电垫与通孔对齐。 坝层位于第一基板和第二表面之间。 坝层朝向通孔突出。 光致抗蚀剂层位于第一表面上，侧壁表面，阻挡层朝向通孔突出，并且在导电垫和阻挡层之间朝向通孔突出。 导电层位于光致抗蚀剂层和导电垫上。

公开(公告)号：US20150099357A1

公开(公告)日：2015-04-09

申请号：US14508989

申请日：2014-10-07

Applicant: XINTEC INC.

Inventor： Chuan-Jin SHIU ,  Tsang-Yu LIU ,  Chih-Wei HO ,  Shih-Hsing CHAN ,  Ching-Jui CHUANG

IPC: H01L23/00

CPC classification number: H01L24/03 ,  H01L21/32139 ,  H01L21/6835 ,  H01L21/78 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68372 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/03009 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/0362 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05583 ,  H01L2224/056 ,  H01L2224/11821 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/0105 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A method of fabricating a wafer-level chip package is provided. First, a wafer with two adjacent chips is provided, the wafer having an upper surface and a lower surface, and one side of each chip includes a conducting pad on the lower surface. A recess and an isolation layer extend from the upper surface to the lower surface, which the recess exposes the conducting pad. A part of the isolation layer is disposed in the recess with an opening to expose the conducting pad. A conductive layer is formed on the isolation layer and the conductive pad, and a photo-resist layer is spray coated on the conductive layer. The photo-resist layer is exposed and developed to expose the conductive layer, and the conductive layer is etched to form a redistribution layer. After stripping the photo-resist layer, a solder layer is formed on the isolation layer and the redistribution layer.

Abstract translation: 提供了制造晶片级芯片封装的方法。 首先，提供具有两个相邻芯片的晶片，所述晶片具有上表面和下表面，并且每个芯片的一侧在下表面上包括导电焊盘。 凹部和隔离层从上表面延伸到下表面，凹部暴露导电垫。 隔离层的一部分设置在具有开口的凹部中以暴露导电垫。 在隔离层和导电焊盘上形成导电层，并且将光致抗蚀剂层喷涂在导电层上。 曝光和显影光致抗蚀剂层以暴露导电层，并且蚀刻导电层以形成再分布层。 在剥离光刻胶层之后，在隔离层和再分布层上形成焊料层。