公开(公告)号：US20130159580A1

公开(公告)日：2013-06-20

申请号：US13516149

申请日：2009-12-17

申请人： YaoZu Dong ,  Yunhong Jiang ,  Kun Tian

发明人： YaoZu Dong ,  Yunhong Jiang ,  Kun Tian

IPC分类号： G06F9/48

CPC分类号： G06F9/45558 ,  G06F9/45545 ,  G06F9/48 ,  G06F9/4812 ,  G06F9/5077 ,  G06F13/24 ,  G06F2009/45595 ,  G06F2213/2408 ,  H04L69/321

摘要： Generally, this disclosure describes systems (and methods) for moderating interrupts in a virtualization environment. An overflow interrupt interval is defined. The overflow interrupt interval is used for triggering activation of an inactive guest so that the guest may respond to a critical event. The guest, including a network application, may be active for a first time interval and inactive for a second time interval. A latency interrupt interval may be defined. The latency interrupt interval is configured for interrupt moderation when the network application associated with a packet flow is active, i.e., when the guest including the network application is active on a processor. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

摘要翻译： 通常，本公开描述了用于调节虚拟化环境中的中断的系统（和方法）。 定义溢出中断间隔。 溢出中断间隔用于触发非活动访客的激活，以便客人可以响应关键事件。 包括网络应用在内的客户端可以在第一时间间隔内处于活动状态，并且在第二时间间隔内不活动。 可以定义延迟中断间隔。 当与分组流相关联的网络应用是活动的时，即当包括网络应用在内的客户在处理器上活动时，延迟中断间隔被配置用于中断节制。 当然，在不偏离本实施例的情况下，可以进行许多替代，变化和修改。

公开(公告)号：US09176770B2

公开(公告)日：2015-11-03

申请号：US13516149

申请日：2009-12-17

申请人： YaoZu Dong ,  Yunhong Jiang ,  Kun Tian

发明人： YaoZu Dong ,  Yunhong Jiang ,  Kun Tian

IPC分类号： G06F13/24 ,  G06F9/48 ,  G06F9/45 ,  G06F9/455 ,  H04L29/08

CPC分类号： G06F9/45558 ,  G06F9/45545 ,  G06F9/48 ,  G06F9/4812 ,  G06F9/5077 ,  G06F13/24 ,  G06F2009/45595 ,  G06F2213/2408 ,  H04L69/321

摘要： Generally, this disclosure describes systems (and methods) for moderating interrupts in a virtualization environment. An overflow interrupt interval is defined. The overflow interrupt interval is used for triggering activation of an inactive guest so that the guest may respond to a critical event. The guest, including a network application, may be active for a first time interval and inactive for a second time interval. A latency interrupt interval may be defined. The latency interrupt interval is configured for interrupt moderation when the network application associated with a packet flow is active, i.e., when the guest including the network application is active on a processor. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

摘要翻译： 通常，本公开描述了用于调节虚拟化环境中的中断的系统（和方法）。 定义溢出中断间隔。 溢出中断间隔用于触发非活动访客的激活，以便客人可以响应关键事件。 包括网络应用在内的客户端可以在第一时间间隔内处于活动状态，并且在第二时间间隔内不活动。 可以定义延迟中断间隔。 当与分组流相关联的网络应用是活动的时，即当包括网络应用在内的客户在处理器上活动时，延迟中断间隔被配置用于中断节制。 当然，在不偏离本实施例的情况下，可以进行许多替代，变化和修改。

公开(公告)号：US20120066676A1

公开(公告)日：2012-03-15

申请号：US12878772

申请日：2010-09-09

申请人： Yao Zu Dong ,  Kun Tian ,  Yunhong Jiang

发明人： Yao Zu Dong ,  Kun Tian ,  Yunhong Jiang

IPC分类号： G06F9/455 ,  G06F12/00

CPC分类号： G06F9/45558 ,  G06F2009/4557 ,  G06F2009/45579

摘要： An embodiment may include circuitry to be comprised at least in part in a first host, and being enabled, when the circuitry is in a first mode of operation, to modify, at least in part, first information maintained, at least in part, by the circuitry and associated, at least in part, with at least one operational state. The circuitry may be disabled from initiating modification to the first information when the circuitry is in a second mode. The circuitry may enter the second mode in response to at least one command. When in the second mode, the circuitry may (1) copy, at least in part, the first information to at least one memory region, (2) replace, at least in part, the first information with second information, and (3) enter at least another operational state associated, at least in part, with the second information.

摘要翻译： 实施例可以包括至少部分地包括在第一主机中的电路，并且当电路处于第一操作模式时，能够至少部分地修改至少部分地由 该电路并且至少部分地具有至少一个操作状态。 当电路处于第二模式时，电路可能被禁止发起对第一信息的修改。 响应于至少一个命令，电路可以进入第二模式。 当在第二模式中，电路可以（1）至少部分地将第一信息复制到至少一个存储器区域，（2）至少部分地用第二信息替换第一信息，以及（3） 至少部分地输入与第二信息相关联的至少另一个操作状态。

公开(公告)号：US08533390B2

公开(公告)日：2013-09-10

申请号：US12872235

申请日：2010-08-31

申请人： Yao Zu Dong ,  Kun Tian ,  Yunhong Jiang

发明人： Yao Zu Dong ,  Kun Tian ,  Yunhong Jiang

IPC分类号： G06F12/00

CPC分类号： G06F5/10 ,  G06F2205/106

摘要： Embodiments of systems, apparatuses, and methods for a circular buffer in a redundant virtualization environment are disclosed. In one embodiment, an apparatus includes a head indicator storage location, an outgoing tail indicator storage location, a buffer tail storage location, and fetch hardware. The head indicator, outgoing tail indicators, and buffer tail indicators are to indicate a head, outgoing tail, and buffer tail, respectively, of a circular buffer. The fetch hardware is to fetch from the head of the circular buffer and advance the head no further than the outgoing tail. The buffer tail is to be filled by software and advanced no further than the head.

摘要翻译： 公开了用于冗余虚拟化环境中的循环缓冲器的系统，装置和方法的实施例。 在一个实施例中，装置包括头部指示器存储位置，输出尾部指示器存储位置，缓冲器尾部存储位置和提取硬件。 头部指示器，输出尾部指示器和缓冲器尾部指示器分别指示循环缓冲器的头部，出口尾部和缓冲器尾部。 提取硬件是从循环缓冲区的头部取出，并且不要将输出尾部提前。 缓冲尾巴要由软件填充，不要超过头。

公开(公告)号：US20120054408A1

公开(公告)日：2012-03-01

申请号：US12872235

申请日：2010-08-31

申请人： Yao Zu (Eddie) Dong ,  Kun Tian ,  Yunhong (Yunhong) Jiang

发明人： Yao Zu (Eddie) Dong ,  Kun Tian ,  Yunhong (Yunhong) Jiang

IPC分类号： G06F12/00 ,  G06F3/00

CPC分类号： G06F5/10 ,  G06F2205/106

摘要： Embodiments of systems, apparatuses, and methods for a circular buffer in a redundant virtualization environment are disclosed. In one embodiment, an apparatus includes a head indicator storage location, an outgoing tail indicator storage location, a buffer tail storage location, and fetch hardware. The head indicator, outgoing tail indicators, and buffer tail indicators are to indicate a head, outgoing tail, and buffer tail, respectively, of a circular buffer. The fetch hardware is to fetch from the head of the circular buffer and advance the head no further than the outgoing tail. The buffer tail is to be filled by software and advanced no further than the head.

摘要翻译： 公开了用于冗余虚拟化环境中的循环缓冲器的系统，装置和方法的实施例。 在一个实施例中，装置包括头部指示器存储位置，输出尾部指示器存储位置，缓冲器尾部存储位置和提取硬件。 头部指示器，输出尾部指示器和缓冲器尾部指示器分别指示循环缓冲器的头部，出口尾部和缓冲器尾部。 提取硬件是从循环缓冲区的头部取出，并且不要将输出尾部提前。 缓冲尾巴要由软件填充，不要超过头。

公开(公告)号：US20140331221A1

公开(公告)日：2014-11-06

申请号：US13882106

申请日：2010-10-28

申请人： Yaozu Dong ,  Kun Tian

发明人： Yaozu Dong ,  Kun Tian

IPC分类号： H04L12/931 ,  G06F9/455

CPC分类号： H04L49/00 ,  G06F9/45533 ,  H04L45/00 ,  H04L63/0245 ,  H04L63/0263

摘要： An apparatus, system, method, and machine-readable medium are disclosed. In one embodiment the apparatus is a network interface controller that includes one virtual function owned by a virtual machine present in the computer system. The controller includes a simple filtering agent that is associated with the first virtual function. The agent enforces simple filter rules for received network packets. The simple filter rules are capable of blocking the network packets from reaching the virtual machine. The apparatus also includes another virtual function that is owned by a virtual machine monitor present in the computer system. The controller also includes a side bounce filtering agent to forward the first network packet to the second virtual function if the first packet is blocked by the at least one of the one or more simple filter rules.

摘要翻译： 公开了一种装置，系统，方法和机器可读介质。 在一个实施例中，该装置是包括由计算机系统中存在的虚拟机拥有的一个虚拟功能的网络接口控制器。 控制器包括与第一虚拟功能相关联的简单过滤代理。 代理对接收到的网络数据包执行简单的过滤规则。 简单的过滤规则能够阻止网络数据包到达虚拟机。 该装置还包括由计算机系统中存在的虚拟机监视器拥有的另一虚拟功能。 如果第一分组被一个或多个简单过滤器规则中的至少一个阻挡，则控制器还包括侧向反弹过滤代理，以将第一网络分组转发到第二虚拟功能。

公开(公告)号：US07360022B2

公开(公告)日：2008-04-15

申请号：US11322008

申请日：2005-12-29

申请人： Kun Tian ,  Yaozu Dong

发明人： Kun Tian ,  Yaozu Dong

IPC分类号： G06F13/28 ,  G06F13/20

CPC分类号： G06F12/0848

摘要： In one embodiment, the present invention includes a method for performing a direct memory access (DMA) operation in a virtualized environment to obtain a page from a memory and store the page in a data cache, and synchronizing the page in the data cache and an instruction cache if the page implicates instruction information, otherwise not synchronizing the page. In this manner, synchronizations may be performed on demand. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括一种用于在虚拟化环境中执行直接存储器访问（DMA）操作以从存储器获得页面并将页面存储在数据高速缓存中并使数据高速缓存中的页面和 指令缓存如果页面涉及指令信息，否则不同步页面。 以这种方式，可以根据需要执行同步。 描述和要求保护其他实施例。

公开(公告)号：US09276875B2

公开(公告)日：2016-03-01

申请号：US13882106

申请日：2010-10-28

申请人： Yaozu Dong ,  Kun Tian

发明人： Yaozu Dong ,  Kun Tian

IPC分类号： G06F13/00 ,  H04L12/931 ,  H04L12/701 ,  G06F9/455 ,  H04L29/06

CPC分类号： H04L49/00 ,  G06F9/45533 ,  H04L45/00 ,  H04L63/0245 ,  H04L63/0263

摘要： An apparatus, system, method, and machine-readable medium are disclosed. In one embodiment the apparatus is a network interface controller that includes one virtual function owned by a virtual machine present in the computer system. The controller includes a simple filtering agent that is associated with the first virtual function. The agent enforces simple filter rules for received network packets. The simple filter rules are capable of blocking the network packets from reaching the virtual machine. The apparatus also includes another virtual function that is owned by a virtual machine monitor present in the computer system. The controller also includes a side bounce filtering agent to forward the first network packet to the second virtual function if the first packet is blocked by the at least one of the one or more simple filter rules.

摘要翻译： 公开了一种装置，系统，方法和机器可读介质。 在一个实施例中，该装置是包括由计算机系统中存在的虚拟机拥有的一个虚拟功能的网络接口控制器。 控制器包括与第一虚拟功能相关联的简单过滤代理。 代理对接收到的网络数据包执行简单的过滤规则。 简单的过滤规则能够阻止网络数据包到达虚拟机。 该装置还包括由计算机系统中存在的虚拟机监视器拥有的另一虚拟功能。 如果第一分组被一个或多个简单过滤器规则中的至少一个阻挡，则控制器还包括侧向反弹过滤代理，以将第一网络分组转发到第二虚拟功能。

公开(公告)号：US20070156969A1

公开(公告)日：2007-07-05

申请号：US11322008

申请日：2005-12-29

申请人： Kun Tian ,  Yaozu Dong

发明人： Kun Tian ,  Yaozu Dong

IPC分类号： G06F13/28

CPC分类号： G06F12/0848

摘要： In one embodiment, the present invention includes a method for performing a direct memory access (DMA) operation in a virtualized environment to obtain a page from a memory and store the page in a data cache, and synchronizing the page in the data cache and an instruction cache if the page implicates instruction information, otherwise not synchronizing the page. In this manner, synchronizations may be performed on demand. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括一种用于在虚拟化环境中执行直接存储器访问（DMA）操作以从存储器获得页面并将页面存储在数据高速缓存中并使数据高速缓存中的页面和 指令缓存如果页面涉及指令信息，否则不同步页面。 以这种方式，可以根据需要执行同步。 描述和要求保护其他实施例。

公开(公告)号：US11768781B2

公开(公告)日：2023-09-26

申请号：US17827556

申请日：2022-05-27

申请人： Niranjan L. Cooray ,  Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Balaji Vembu ,  Pattabhiraman K ,  David Puffer ,  David J. Cowperthwaite ,  Rajesh M. Sankaran ,  Satyeshwar Singh ,  Sameer Kp ,  Ankur N. Shah ,  Kun Tian

发明人： Niranjan L. Cooray ,  Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Balaji Vembu ,  Pattabhiraman K ,  David Puffer ,  David J. Cowperthwaite ,  Rajesh M. Sankaran ,  Satyeshwar Singh ,  Sameer Kp ,  Ankur N. Shah ,  Kun Tian

IPC分类号： G06F9/455 ,  G06F9/50 ,  G06F13/16 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/0802 ,  G06F13/40

CPC分类号： G06F13/16 ,  G06F12/0802 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F13/4068 ,  G06F2212/1024 ,  G06F2212/302 ,  G06F2212/60 ,  G06F2212/68

摘要： An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.