Abstract:
When a signal output by a solid-state image sensing device is clamped to a predetermined reference potential, a high voltage generated in a transfer suspension period after the clamping as generally supplied to an A/D converter is generated. A sample/hold output Va is clamped to a clamp level Vref over a period of time between a halfway point of time of a signal of a picture element preceding ahead by one line and the end of an inhibit period of transfer clocks of a signal output by an empty transmission unit via a first clamp pulse and a sample/hold output for the second picture element, or a subsequent one of an OPB unit is clamped to the clamp level via a second clamp pulse to prevent a signal output from exceeding a reference voltage from being supplied to an A/D converter at a later stage.
Abstract:
When a signal output by a solid-state image sensing device is clamped to a predetermined reference potential, a high voltage generated in a transfer suspension period after the clamping as generally supplied to an A/D converter is generated. A sample/hold output Va is clamped to a clamp level Vref over a period of time between a halfway point of time of a signal of a picture element preceding ahead by one line and the end of an inhibit period of transfer clocks of a signal output by an empty transmission unit via a first clamp pulse and a sample/hold output for the second picture element, or a subsequent one of an OPB unit is clamped to the clamp level via a second clamp pulse to prevent a signal output from exceeding a reference voltage from being supplied to an A/D converter at a later stage.
Abstract:
When a signal output by a solid-state image sensing device is clamped to a predetermined reference potential, a high voltage generated in a transfer suspension period after the clamping as generally supplied to an A/D converter is generated. A sample/hold output Va is clamped to a clamp level Vref over a period of time between a halfway point of time of a signal of a picture element preceding ahead by one line and the end of an inhibit period of transfer clocks of a signal output by an empty transmission unit via a first clamp pulse and a sample/hold output for the second picture element, or a subsequent one of an OPB unit is clamped to the clamp level via a second clamp pulse to prevent a signal output from exceeding a reference voltage from being supplied to an A/D converter at a later stage.
Abstract:
In a floating diffusion output type or a floating gate output type charge-to-voltage converter, the floating diffusion or the floating gate is coupled to one or more diffusion regions by means of one or more switch elements, and such elements are selectively turned on or off in such a manner that the the charge-to-voltage conversion factor is raised to obtain a great voltage amplitude when a small quantity of signal charge is input, or the conversion factor is lowered to obtain a small voltage amplitude when a large quantity of signal charge is input.
Abstract:
An adaptive peak value detector, wherein the peak value for a peak hold section is detected, the peak hold section being selected by a peak hold control circuit. A solid-state imaging sensor generates pixel signals representative of an image and the peak value of portions of the pixel signals is detected. The exposure time of the sensor is adjusted as a function of the detected peak value and auto-focusing of the image for the camera is carried out on the basis of the image received during the adjusted exposure time.
Abstract:
It is an object of the present invention to provide a solid-state image sensing device with a vertical shutter structure allowing the size of the solid-state image sensing device with ease. An electric-charge exhausting unit is provided on the same side of a sensor array comprising a plurality of sensor units arranged to form a straight line as an electric-charge transferring unit wherein the electric-charge exhausting unit comprising an electric-charge exhaust drain having a shape resembling an island and an electric-charge exhausting gate with a bent shape surrounding the electric-charge exhaust drain is provided in such a way that the electric-charge exhausting unit is in contact with a first region of a read gate, and only one electric-charge exhausting unit is provided for each pair of sensor units adjacent to each other.
Abstract:
A linear sensor for sampling vertically opposed pixels of a plurality of vertically arranged sensor rows substantially at a time. A plurality of horizontal transfer registers and a plurality of shift gates are provided to oppose the plurality of sensor rows. A vertical transfer register is provided at one end of the plurality of horizontal transfer registers. In the vertical transfer register, the signal charges which have been transferred by the plurality of horizontal transfer registers are transferred sequentially in vertical direction. A charge/voltage converter unit is provided at the output of the vertical transfer register. The signal charges accumulated in the vertically opposed pixels are sequentially transferred to the charge/voltage converter unit in a repetitive manner.
Abstract:
The photometric sensor of the present invention includes a plurality of photoelectric conversion elements which accumulate electric charge according to the intensity of the light which is incident upon them; a CCD shift register, comprising a plurality of CCD (Charge Coupled Device) elements which correspond respectively to the plurality of photoelectric conversion elements, and at least one relay CCD element which does not correspond to any one of the photoelectric conversion elements, and which reads in the accumulated electric charges from the plurality of photoelectric conversion elements to the plurality of CCD elements and transmits them via the relay CCD element; a charge to voltage conversion circuit which converts the accumulated electric charges transmitted from the CCD shift register into photometric signals and outputs them in order; and a timing signal generation circuit which, when the photometric signals from the charge to voltage conversion circuit originating from the plurality of photoelectric conversion elements are output, outputs in synchronism with this output a timing signal, and, when a signal from the charge to voltage conversion circuit originating from the relay CCD element is output, does not output the timing signal in synchronism with this output.
Abstract:
An input structure of CCD comprises a primary register having an input gate and a source region and an automatic biasing system which generates a feedback signal to be fed back to input of the primary register. The output of the automatic biasing system is connected to one of the input gate and the source of the primary register for supplying the feedback signal thereto for adjusting input bias level of the primary register. The other one of the input gate and the source is connected to an information signal input terminal to receive therefrom an information signal to be transferred therethrough.
Abstract:
When a signal output by a solid-state image sensing device is clamped to a predetermined reference potential, a high voltage generated in a transfer suspension period after the clamping as generally supplied to an A/D converter is generated. A sample/hold output Va is clamped to a clamp level Vref over a period of time between a halfway point of time of a signal of a picture element preceding ahead by one line and the end of an inhibit period of transfer clocks of a signal output by an empty transmission unit via a first clamp pulse and a sample/hold output for the second picture element, or a subsequent one of an OPB unit is clamped to the clamp level via a second clamp pulse to prevent a signal output from exceeding a reference voltage from being supplied to an A/D converter at a later stage.