公开(公告)号：US07737026B2

公开(公告)日：2010-06-15

申请号：US11693153

申请日：2007-03-29

申请人： Ying Li ,  Keith Kwong-Hon Wong

发明人： Ying Li ,  Keith Kwong-Hon Wong

IPC分类号： H01L21/4763

CPC分类号： H01L23/53238 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76865 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming an interconnection in a semiconductor device includes forming a first liner in a dielectric layer therein; depositing a tungsten filler on top of the first liner; performing chemical mechanical planarization (CMP) to smooth out and remove the first liner and tungsten filler from the semiconductor's exposed surface; selectively removing the first liner and tungsten filler in the via; wherein the selective removing results in the first liner and the tungsten filler being removed in an upper region of the via; forming a second liner in the upper region of the via and tungsten filler; selectively removing the second liner from the tungsten filler; forming a copper seed layer on top of the tungsten filler; depositing a copper filler on top of the copper seed layer; and performing chemical CMP to smooth out and remove the second liner and copper filler from the semiconductor's exposed surface.

摘要翻译： 在半导体器件中形成互连的方法包括在其中的介电层中形成第一衬垫; 在第一衬垫的顶部上沉积钨填料; 进行化学机械平面化（CMP）以平滑并从半导体的暴露表面去除第一衬里和钨填料; 选择性地去除通孔中的第一衬垫和钨填料; 其中所述选择性去除导致所述第一衬里和所述钨填料在所述通孔的上部区域中被去除; 在所述通孔和钨填料的上部区域中形成第二衬垫; 从所述钨填料选择性地去除所述第二衬里; 在钨填料的顶部形成铜籽晶层; 在铜籽晶层的顶部沉积铜填料; 并进行化学CMP以平滑并从半导体的露出表面去除第二衬里和铜填料。

公开(公告)号：US20080237869A1

公开(公告)日：2008-10-02

申请号：US11693153

申请日：2007-03-29

申请人： Ying Li ,  Keith Kwong-Hon Wong

发明人： Ying Li ,  Keith Kwong-Hon Wong

IPC分类号： H01L23/522

CPC分类号： H01L23/53238 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76865 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming an interconnection in a semiconductor device includes forming a first liner in a dielectric layer therein; depositing a tungsten filler on top of the first liner; performing chemical mechanical planarization (CMP) to smooth out and remove the first liner and tungsten filler from the semiconductor's exposed surface; selectively removing the first liner and tungsten filler in the via; wherein the selective removing results in the first liner and the tungsten filler being removed in an upper region of the via; forming a second liner in the upper region of the via and tungsten filler; selectively removing the second liner from the tungsten filler; forming a copper seed layer on top of the tungsten filler; depositing a copper filler on top of the copper seed layer; and performing chemical CMP to smooth out and remove the second liner and copper filler from the semiconductor's exposed surface.

摘要翻译： 在半导体器件中形成互连的方法包括在其中的介电层中形成第一衬垫; 在第一衬垫的顶部上沉积钨填料; 进行化学机械平面化（CMP）以平滑并从半导体的暴露表面去除第一衬里和钨填料; 选择性地去除通孔中的第一衬垫和钨填料; 其中所述选择性去除导致所述第一衬里和所述钨填料在所述通孔的上部区域中被去除; 在所述通孔和钨填料的上部区域中形成第二衬垫; 从所述钨填料选择性地去除所述第二衬里; 在钨填料的顶部形成铜籽晶层; 在铜籽晶层的顶部沉积铜填料; 并进行化学CMP以平滑并从半导体的露出表面去除第二衬里和铜填料。

公开(公告)号：US07514271B2

公开(公告)日：2009-04-07

申请号：US11694183

申请日：2007-03-30

申请人： Michael C. Gaidis ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  John K. DeBrosse ,  Louis L. C. Hsu ,  Carl Radens ,  Keith Kwong-Hon Wong ,  Chih-Chao Yang

发明人： Michael C. Gaidis ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  John K. DeBrosse ,  Louis L. C. Hsu ,  Carl Radens ,  Keith Kwong-Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L21/00 ,  G11C5/12 ,  G11C11/14

CPC分类号： G11C19/0841 ,  B82Y10/00 ,  G11C5/02 ,  G11C11/161 ,  G11C11/1675 ,  Y10T29/53165

摘要： A method of forming a magnetic domain wall memory apparatus with write/read capability includes forming a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location: forming a magnetic read element associated with each of the shift register structures: and forming a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a write wire having a constriction therein, the constriction located at a point corresponding to the location of one of the plurality of discontinuities in the associated shift register structure.

摘要翻译： 形成具有写入/读取能力的磁畴壁存储装置的方法包括形成多个共面移位寄存器结构，每个包括由其中具有多个磁畴的铁磁材料形成的细长轨道，移位寄存器结构还具有多个 其中的不连续性以便于域壁位置：形成与每个移位寄存器结构相关联的磁读取元件;以及形成与每个移位寄存器结构相关联的磁写元件，所述磁写入元件还包括具有收缩的写入线 其中，所述收缩部位于与相关联的移位寄存器结构中的所述多个不连续之一的位置相对应的点处。

公开(公告)号：US08009453B2

公开(公告)日：2011-08-30

申请号：US12136089

申请日：2008-06-10

申请人： Michael C. Gaidis ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  John K. DeBrosse ,  Louis L. C. Hsu ,  Carl Radens ,  Keith Kwong-Hon Wong ,  Chih-Chao Yang

发明人： Michael C. Gaidis ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  John K. DeBrosse ,  Louis L. C. Hsu ,  Carl Radens ,  Keith Kwong-Hon Wong ,  Chih-Chao Yang

IPC分类号： G11C19/08 ,  G11C19/38

CPC分类号： G11C19/0841 ,  B82Y10/00 ,  G11C5/02 ,  G11C11/161 ,  G11C11/1675 ,  Y10T29/53165

摘要： A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a write wire having a constriction therein, the constriction located at a point corresponding to the location of the plurality of discontinuities in the associated shift register structure.

摘要翻译： 具有写入/读取功能的磁畴壁存储装置包括多个共面移位寄存器结构，每个包括由其中具有多个磁畴的铁磁材料形成的细长轨道，移位寄存器结构还具有多个不连续性，以便于 域墙位置; 与每个移位寄存器结构相关联的磁读取元件; 以及与所述移位寄存器结构中的每一个相关联的磁写元件，所述磁写入元件还包括其中具有收缩部的写入线，所述收缩部位于与相关联的移位寄存器结构中的所述多个不连续点的位置对应的点处。

公开(公告)号：US07457097B2

公开(公告)日：2008-11-25

申请号：US10710653

申请日：2004-07-27

申请人： David J. Bain ,  Christopher S. Birchard ,  Keith Kwong-Hon Wong

发明人： David J. Bain ,  Christopher S. Birchard ,  Keith Kwong-Hon Wong

IPC分类号： H02N13/00 ,  H02H1/00

CPC分类号： H01L21/6831

摘要： An electrostatic wafer holding apparatus includes an electrostatic chucking pedestal and a bi-directional backside conduit in fluid communication with a backside of the chucking pedestal. The bi-directional backside conduit is in fluid communication with a backside carrier gas supply line, and is further in fluid communication with a vacuum supply line.

摘要翻译： 静电晶片保持装置包括静电吸盘基座和与卡盘座背面流体连通的双向背面导管。 双向背面导管与后侧载体气体供应管线流体连通，并且还与真空供应管线流体连通。

公开(公告)号：US07144490B2

公开(公告)日：2006-12-05

申请号：US10707047

申请日：2003-11-18

申请人： Tien-Jen Cheng ,  David E. Eichstadt ,  Jonathan H. Griffith ,  Sarah H. Knickerbocker ,  Rosemary A. Previti-Kelly ,  Roger A. Quon ,  Kamalesh K. Srivastava ,  Keith Kwong-Hon Wong

发明人： Tien-Jen Cheng ,  David E. Eichstadt ,  Jonathan H. Griffith ,  Sarah H. Knickerbocker ,  Rosemary A. Previti-Kelly ,  Roger A. Quon ,  Kamalesh K. Srivastava ,  Keith Kwong-Hon Wong

IPC分类号： C25D5/02 ,  C25D7/12

CPC分类号： H01L24/13 ,  C25D5/022 ,  C25D5/12 ,  C25D7/123 ,  H01L24/11 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05558 ,  H01L2224/05562 ,  H01L2224/05644 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0001 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2224/29099 ,  H01L2224/05552 ,  H01L2924/00014 ,  H01L2924/013

摘要： A method for selective electroplating of a semiconductor input/output (I/O) pad includes forming a titanium-tungsten (TiW) layer over a passivation layer on a semiconductor substrate, the TiW layer further extending into an opening formed in the passivation layer for exposing the I/O pad, such that the TiW layer covers sidewalls of the opening and a top surface of the I/O pad. A seed layer is formed over the TiW layer, and portions of the seed layer are selectively removed such that remaining seed layer material corresponds to a desired location of interconnect metallurgy for the I/O pad. At least one metal layer is electroplated over the remaining seed layer material, using the TiW layer as a conductive electroplating medium.

摘要翻译： 一种用于半导体输入/输出（I / O）焊盘的选择性电镀的方法包括在半导体衬底上的钝化层上形成钛 - 钨（TiW）层，所述TiW层进一步延伸到形成在钝化层中的开口中 暴露I / O焊盘，使得TiW层覆盖开口的侧壁和I / O焊盘的顶表面。 在TiW层上形成种子层，并且选择性地去除种子层的部分，使得剩余的种子层材料对应于用于I / O焊盘的互连冶金的期望位置。 使用TiW层作为导电电镀介质，在剩余的种子层材料上电镀至少一层金属层。

公开(公告)号：US08023305B2

公开(公告)日：2011-09-20

申请号：US12136091

申请日：2008-06-10

申请人： Michael C. Gaidis ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  John K. DeBrosse ,  Louis L. C. Hsu ,  Carl Radens ,  Keith Kwong-Hon Wong ,  Chih-Chao Yang

发明人： Michael C. Gaidis ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  John K. DeBrosse ,  Louis L. C. Hsu ,  Carl Radens ,  Keith Kwong-Hon Wong ,  Chih-Chao Yang

IPC分类号： G11C19/02 ,  G11C19/08

CPC分类号： G11C19/0841 ,  B82Y10/00 ,  G11C5/02 ,  G11C11/161 ,  G11C11/1675 ,  Y10T29/53165

摘要： A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a single write wire having a longitudinal axis substantially orthogonal to a longitudinal axis of each of the coplanar shift register structures.

摘要翻译： 具有写入/读取功能的磁畴壁存储装置包括多个共面移位寄存器结构，每个包括由其中具有多个磁畴的铁磁材料形成的细长轨道，移位寄存器结构还具有多个不连续性，以便于 域墙位置; 与每个移位寄存器结构相关联的磁读取元件; 以及与所述移位寄存器结构中的每一个相关联的磁写元件，所述磁写入元件还包括单个写入线，所述单个写入线的纵轴基本上与所述共面移位寄存器结构中的每一个的纵向轴线正交。

公开(公告)号：US20090034151A1

公开(公告)日：2009-02-05

申请号：US12248105

申请日：2008-10-09

申请人： David J. Bain ,  Christopher S. Birchard ,  Keith Kwong-Hon Wong

发明人： David J. Bain ,  Christopher S. Birchard ,  Keith Kwong-Hon Wong

IPC分类号： H01L21/683

CPC分类号： H01L21/6831

摘要： An electrostatic wafer holding apparatus includes an electrostatic chucking pedestal and a bi-directional backside conduit in fluid communication with a backside of the chucking pedestal. The bi-directional backside conduit is in fluid communication with a backside carrier gas supply line, and is further in fluid communication with a vacuum supply line.

摘要翻译： 静电晶片保持装置包括静电吸盘基座和与卡盘座背面流体连通的双向背面导管。 双向背面导管与后侧载体气体供应管线流体连通，并且还与真空供应管线流体连通。

公开(公告)号：US06426903B1

公开(公告)日：2002-07-30

申请号：US09923721

申请日：2001-08-07

申请人： Lawrence A. Clevenger ,  Louis Lu-Chen Hsu ,  Li-Kong Wang ,  Keith Kwong-Hon Wong

发明人： Lawrence A. Clevenger ,  Louis Lu-Chen Hsu ,  Li-Kong Wang ,  Keith Kwong-Hon Wong

IPC分类号： G11C700

CPC分类号： G11C29/80 ,  Y10S977/888 ,  Y10S977/943

摘要： A static redundancy arrangement for a circuit using a focused ion beam anti-fuse methodology which reduces the circuit layout area and the switching activity compared to a prior art dynamic redundancy scheme, resulting in less power, a simpler design and higher speed. Focused ion beam anti-fuse methodology is used to program redundancy for circuits, particularly wide I/O embedded DRAM macros. An anti-fuse array circuit is comprised of a plurality of anti-fuse programming elements, each of which comprises a latch circuit controlled by a set input signal, and an anti-fuse device which is programmed by a focused ion beam.

摘要翻译： 使用聚焦离子束反熔丝方法的电路的静态冗余布置，与现有技术的动态冗余方案相比，其减小了电路布局面积和开关活动，导致较少的功率，更简单的设计和更高的速度。 聚焦离子束反熔丝方法用于编程电路冗余，特别是宽I / O嵌入式DRAM宏。 反熔丝阵列电路由多个反熔丝编程元件组成，每个反熔丝编程元件包括由设定的输入信号控制的锁存电路和由聚焦离子束编程的反熔丝器件。