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    LINER FOR TUNGSTEN/SILICON DIOXIDE INTERFACE IN MEMORY
    1.
    发明申请
    LINER FOR TUNGSTEN/SILICON DIOXIDE INTERFACE IN MEMORY 有权
    内存中的TUNGSTEN /二氧化硅界面

    公开(公告)号：US20090085087A1

    公开(公告)日：2009-04-02

    申请号：US11863734

    申请日：2007-09-28

    申请人： Yoichiro Tanaka ,  Steven J. Radigan ,  Usha Raghuram

    发明人： Yoichiro Tanaka ,  Steven J. Radigan ,  Usha Raghuram

    IPC分类号： H01L29/788 ,  H01L21/4763

    CPC分类号： H01L27/101 ,  H01L27/1021

    摘要： A semiconductor wafer assembly includes a base of dielectric. A layer of silicon is deposited thereover. A metal hard mask is deposited over the silicon. A dielectric hard mask is deposited over the metal hard mask. Photoresist is deposited over the dielectric hard mask, whereby a plurality of sacrificial columns is formed from the layer of metal hard mask through the photoresist such that the sacrificial columns extend out from the silicon layer. An interface layer is disposed between the layer of conductive material and the layer of hard mask to enhance adhesion between each of the plurality of sacrificial columns and the layer of conductive material to optimize the formation of junction diodes out of the silicon by preventing the plurality of sacrificial columns from being detached from the layer of silicon prematurely due to the sacrificial columns peeling or falling off.

    摘要翻译： 半导体晶片组件包括电介质基体。 一层硅沉积在其上。 金属硬掩模沉积在硅上。 在金属硬掩模上沉积电介质硬掩模。 光致抗蚀剂沉积在电介质硬掩模上，由此通过光致抗蚀剂从金属硬掩模层形成多个牺牲柱，使得牺牲柱从硅层延伸出来。 界面层设置在导电材料层和硬掩模层之间，以增强多个牺牲柱和导电材料层之间的粘附力，以通过防止多个 牺牲柱由于牺牲柱脱落或脱落而过早地与硅层分离。

    Liner for tungsten/silicon dioxide interface in memory
    2.
    发明授权
    Liner for tungsten/silicon dioxide interface in memory 有权
    内存中用于钨/二氧化硅界面的衬垫

    公开(公告)号：US08071475B2

    公开(公告)日：2011-12-06

    申请号：US11863734

    申请日：2007-09-28

    申请人： Yoichiro Tanaka ,  Steven J. Radigan ,  Usha Raghuram

    发明人： Yoichiro Tanaka ,  Steven J. Radigan ,  Usha Raghuram

    IPC分类号： H01L21/44

    CPC分类号： H01L27/101 ,  H01L27/1021

    摘要： A semiconductor wafer assembly includes a base of dielectric. A layer of silicon is deposited thereover. A metal hard mask is deposited over the silicon. A dielectric hard mask is deposited over the metal hard mask. Photoresist is deposited over the dielectric hard mask, whereby a plurality of sacrificial columns is formed from the layer of metal hard mask through the photoresist such that the sacrificial columns extend out from the silicon layer. An interface layer is disposed between the layer of conductive material and the layer of hard mask to enhance adhesion between each of the plurality of sacrificial columns and the layer of conductive material to optimize the formation of junction diodes out of the silicon by preventing the plurality of sacrificial columns from being detached from the layer of silicon prematurely due to the sacrificial columns peeling or falling off.

    摘要翻译： 半导体晶片组件包括电介质基体。 一层硅沉积在其上。 金属硬掩模沉积在硅上。 电介质硬掩模沉积在金属硬掩模上。 光致抗蚀剂沉积在电介质硬掩模上，由此通过光致抗蚀剂从金属硬掩模层形成多个牺牲柱，使得牺牲柱从硅层延伸出来。 界面层设置在导电材料层和硬掩模层之间，以增强多个牺牲柱和导电材料层之间的粘附力，以通过防止多个 牺牲柱由于牺牲柱脱落或脱落而过早地与硅层分离。

    CONDUCTIVE HARD MASK TO PROTECT PATTERNED FEATURES DURING TRENCH ETCH
    3.
    发明申请
    CONDUCTIVE HARD MASK TO PROTECT PATTERNED FEATURES DURING TRENCH ETCH 审中-公开
    导电硬掩模，以保护在TRENCH ETCH期间的图案特征

    公开(公告)号：US20090273022A1

    公开(公告)日：2009-11-05

    申请号：US12502796

    申请日：2009-07-14

    申请人： Steven J. Radigan ,  Usha Raghuram ,  Samuel V. Dunton ,  Michael W. Konevecki

    发明人： Steven J. Radigan ,  Usha Raghuram ,  Samuel V. Dunton ,  Michael W. Konevecki

    IPC分类号： H01L27/105 ,  H01L21/8234 ,  H01L21/822 ,  H01L27/06

    CPC分类号： H01L23/5252 ,  H01L27/1021 ,  H01L29/6609 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A monolithic three dimensional memory array is formed by a method that includes forming a first memory level above a substrate by i) forming a plurality of first substantially parallel conductors extending in a first direction, ii) forming first pillars above the first conductors, each first pillar comprising a first conductive layer or layerstack above a vertically oriented diode, the first pillars formed in a single photolithography step, iii) depositing a first dielectric layer above the first pillars, and iv) etching a plurality of substantially parallel first trenches in the first dielectric layer, the first trenches extending in a second direction, wherein, after the etching step, the lowest point in the trenches is above the lowest point of the first conductive layer or layerstack, wherein the first conductive layer or layerstack does not comprise a resistivity-switching metal oxide or nitride. The method also includes monolithically forming a second memory level above the first memory level. Other aspects are also described.

    摘要翻译： 单片三维存储器阵列通过一种方法形成，该方法包括通过在第一方向上形成多个沿第一方向延伸的多个第一基本上平行的导体形成第一存储器电平，ii）在第一导体上方形成第一柱， 柱，其包括在垂直取向的二极管上方的第一导电层或层堆叠，在单个光刻步骤中形成的第一柱，iii）在第一柱上方沉积第一电介质层，以及iv）在第一栅极中蚀刻多个基本上平行的第一沟槽 所述第一沟槽在第二方向上延伸，其中在所述蚀刻步骤之后，所述沟槽中的最低点高于所述第一导电层或层堆叠的最低点，其中所述第一导电层或所述层堆叠不包含电阻率 开关金属氧化物或氮化物。 该方法还包括在第一存储器级上方单片地形成第二存储器级。 还描述了其他方面。

    Process to remove Ni and Pt residues for NiPtSi applications using chlorine gas
    6.
    发明授权
    Process to remove Ni and Pt residues for NiPtSi applications using chlorine gas 有权
    使用氯气去除NiPtSi应用的Ni和Pt残留物的工艺

    公开(公告)号：US08466058B2

    公开(公告)日：2013-06-18

    申请号：US13295333

    申请日：2011-11-14

    申请人： Anh Duong ,  John Foster ,  Olov Karlsson ,  James Mavrinac ,  Usha Raghuram

    发明人： Anh Duong ,  John Foster ,  Olov Karlsson ,  James Mavrinac ,  Usha Raghuram

    IPC分类号： H01L21/44

    CPC分类号： H01L21/324 ,  H01L21/02068 ,  H01L21/28 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/67028 ,  H01L21/67057 ,  H01L29/665

    摘要： The invention discloses a method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process. Post silicidation residues of nickel and platinum may not be removed adequately just by an aqua regia solution (comprising a mixture of nitric acid and hydrochloric acid). Therefore, embodiments of the invention provide a multi-step residue cleaning, comprising exposing the substrate to an aqua regia solution, followed by an exposure to a chlorine gas or a solution comprising dissolved chlorine gas, which may further react with remaining platinum residues, rendering it more soluble in aqueous solution and thereby dissolving it from the surface of the substrate.

    摘要翻译： 本发明公开了一种在镍铂硅化过程中清除半导体衬底的残留物的方法。 镍和铂的后硅化残留物只能通过王水溶液（包括硝酸和盐酸的混合物）而被充分除去。 因此，本发明的实施方案提供多步残留物清洗，包括将底物暴露于王水溶液，随后暴露于氯气或包含溶解的氯气的溶液中，其可进一步与剩余的铂残基反应，使得 它更可溶于水溶液，从而从基底表面溶解。

    PILLAR DEVICES AND METHODS OF MAKING THEREOF
    7.
    发明申请
    PILLAR DEVICES AND METHODS OF MAKING THEREOF 有权
    支柱装置及其制造方法

    公开(公告)号：US20110136326A1

    公开(公告)日：2011-06-09

    申请号：US13026381

    申请日：2011-02-14

    申请人： Vance DUNTON ,  S. Brad Herner ,  Paul Wai Kie Poon ,  Chuanbin Pan ,  Michael Chan ,  Michael Konevecki ,  Usha Raghuram

    发明人： Vance DUNTON ,  S. Brad Herner ,  Paul Wai Kie Poon ,  Chuanbin Pan ,  Michael Chan ,  Michael Konevecki ,  Usha Raghuram

    IPC分类号： H01L21/36

    CPC分类号： H01L27/1021 ,  H01L29/8613 ,  H01L29/8615 ,  H01L29/868

    摘要： A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first semiconductor layer in the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the first semiconductor layer, such that first conductivity type second portions of the first semiconductor layer remain in lower portions of the plurality of openings in the insulating layer, and upper portions of the plurality of openings in the insulating layer remain unfilled. The method also includes forming a second semiconductor layer in the upper portions of the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the second semiconductor layer located over the insulating layer. The second conductivity type second portions of the second semiconductor layer remain in upper portions of the plurality of openings in the insulating layer to form a plurality of pillar shaped diodes in the plurality of openings.

    摘要翻译： 制造半导体器件的方法包括提供包含多个开口的绝缘层，在绝缘层中的多个开口中并在绝缘层之上形成第一半导体层，以及去除第一半导体层的第一部分， 第一半导体层的第一导电类型的第二部分保留在绝缘层中的多个开口的下部，并且绝缘层中的多个开口的上部保持未填充。 该方法还包括在绝缘层中的多个开口的上部和绝缘层上形成第二半导体层，以及去除位于绝缘层之上的第二半导体层的第一部分。 第二半导体层的第二导电类型的第二部分保留在绝缘层中的多个开口的上部，以在多个开口中形成多个柱状二极管。

    Method for reducing dielectric overetch using a dielectric etch stop at a planar surface
    9.
    发明授权
    Method for reducing dielectric overetch using a dielectric etch stop at a planar surface 有权
    在平坦表面使用电介质蚀刻停止来减少介电过程的方法

    公开(公告)号：US07790607B2

    公开(公告)日：2010-09-07

    申请号：US11923687

    申请日：2007-10-25

    申请人： Samuel V. Dunton ,  Usha Raghuram ,  Christopher J. Petti

    发明人： Samuel V. Dunton ,  Usha Raghuram ,  Christopher J. Petti

    IPC分类号： H01L21/4763

    CPC分类号： H01L27/1021 ,  H01L21/76802 ,  H01L21/76829 ,  Y10S438/90

    摘要： A substantially planar surface coexposes conductive or semiconductor features and a dielectric etch stop material. A second dielectric material, different from the dielectric etch stop material, is deposited on the substantially planar surface. A selective etch etches a hole or trench in the second dielectric material, so that the etch stops on the conductive or semiconductor feature and the dielectric etch stop material. In a preferred embodiment the substantially planar surface is formed by filling gaps between the conductive or semiconductor features with a first dielectric such as oxide, recessing the oxide, filling with a second dielectric such as nitride, then planarizing to coexpose the nitride and the conductive or semiconductor features.

    摘要翻译： 基本平坦的表面共同导电或半导体特征和介电蚀刻停止材料。 不同于介电蚀刻停止材料的第二电介质材料沉积在基本平坦的表面上。 选择性蚀刻蚀刻第二介电材料中的孔或沟槽，使得蚀刻停止在导电或半导体特征和电介质蚀刻停止材料上。 在优选实施例中，通过将导电或半导体特征之间的间隙填充到诸如氧化物的第一电介质，使氧化物凹陷，用第二电介质（例如氮化物）填充，然后平坦化以共存氮化物和导电或 半导体功能。