公开(公告)号：US20120080677A1

公开(公告)日：2012-04-05

申请号：US13039096

申请日：2011-03-02

申请人： Yong-Su LEE ,  Su-Hyoung KANG

发明人： Yong-Su LEE ,  Su-Hyoung KANG

IPC分类号： H01L29/786 ,  H01L21/28

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L29/66765 ,  H01L29/7869

摘要： A manufacturing method of a thin film transistor array panel includes forming a gate line including a gate electrode on a substrate; forming a gate insulating layer on the gate line; forming a semiconductor layer on the gate insulating layer; forming a data line including a data conductive layer pattern on the semiconductor layer and crossing the gate line; forming a planarization layer on the data conductive layer pattern; dry-etching the planarization layer to expose a portion of the data conductive layer pattern overlapping the gate electrode; wet-etching the exposed data conductive layer pattern; and exposing a portion of the semiconductor layer overlapping the gate electrode.

摘要翻译： 薄膜晶体管阵列面板的制造方法包括在基板上形成包括栅电极的栅极线; 在栅极线上形成栅极绝缘层; 在所述栅极绝缘层上形成半导体层; 在半导体层上形成数据线，该数据线包括数据导电层图案并与栅极线交叉; 在所述数据导电层图案上形成平坦化层; 干蚀刻平坦化层以暴露与栅电极重叠的数据导电层图案的一部分; 湿蚀刻暴露的数据导电层图案; 以及暴露半导体层与栅电极重叠的部分。

公开(公告)号：US20130001573A1

公开(公告)日：2013-01-03

申请号：US13418172

申请日：2012-03-12

申请人： Yong-Su LEE ,  Yoon-Ho KHANG ,  Se-Hwan YU ,  Su-Hyoung KANG

发明人： Yong-Su LEE ,  Yoon-Ho KHANG ,  Se-Hwan YU ,  Su-Hyoung KANG

IPC分类号： H01L29/786 ,  H01L21/36

CPC分类号： H01L29/78642 ,  H01L29/41733 ,  H01L29/41741 ,  H01L29/41775 ,  H01L29/45 ,  H01L29/66666 ,  H01L29/6675 ,  H01L29/78606 ,  H01L29/7869

摘要： A thin film transistor including a gate electrode, a semiconductor layer, a gate insulating layer, a source electrode, a drain electrode and a graphene pattern. The semiconductor layer overlaps with the gate electrode. The gate insulating layer is disposed between the gate electrode and the semiconductor layer. The source electrode overlaps with the semiconductor layer. The drain electrode overlaps with the semiconductor layer. The drain electrode is spaced apart from the source electrode. The graphene pattern is disposed between the semiconductor layer and at least one of the source electrode and the drain electrode.

摘要翻译： 一种薄膜晶体管，包括栅电极，半导体层，栅极绝缘层，源电极，漏电极和石墨烯图案。 半导体层与栅电极重叠。 栅极绝缘层设置在栅电极和半导体层之间。 源电极与半导体层重叠。 漏电极与半导体层重叠。 漏电极与源电极间隔开。 石墨烯图案设置在半导体层与源电极和漏电极中的至少一个之间。

公开(公告)号：US20130027627A1

公开(公告)日：2013-01-31

申请号：US13544751

申请日：2012-07-09

申请人： Su-Hyoung KANG ,  Yoonho Khang ,  Sangho Park ,  Jungkyu Lee ,  Chong Sup Chang

发明人： Su-Hyoung KANG ,  Yoonho Khang ,  Sangho Park ,  Jungkyu Lee ,  Chong Sup Chang

IPC分类号： H01L29/786 ,  G02F1/136 ,  H01L21/336

CPC分类号： H01L29/41733 ,  G02F1/1368 ,  H01L27/124 ,  H01L29/78642 ,  H01L29/78696

摘要： A display apparatus includes a thin film transistor substrate, a substrate facing the thin film transistor substrate, and a liquid crystal layer. The thin film transistor substrate includes an insulating substrate, a gate electrode disposed on a surface of the insulating substrate, a gate insulating layer covering the gate electrode, a semiconductor layer disposed on the gate insulating layer, a source electrode disposed on the semiconductor layer, and a drain electrode disposed on the semiconductor layer and spaced apart from the source electrode. One of the source electrode and the drain electrode is spaced apart from the gate electrode in a plan view. The gate electrode includes a side surface inclined with respect to the surface of the insulating substrate and is partially overlapped with a portion of the source electrode or the drain electrode in a direction perpendicular to the side surface of the gate electrode.

摘要翻译： 显示装置包括薄膜晶体管基板，面向薄膜晶体管基板的基板和液晶层。 薄膜晶体管基板包括绝缘基板，设置在绝缘基板的表面上的栅极电极，覆盖栅电极的栅极绝缘层，设置在栅极绝缘层上的半导体层，设置在半导体层上的源电极， 以及设置在半导体层上并与源电极间隔开的漏电极。 在平面图中，源电极和漏极之一与栅电极间隔开。 栅极包括相对于绝缘基板的表面倾斜的侧表面，并且在与栅电极的侧表面垂直的方向上与源电极或漏电极的一部分重叠。

公开(公告)号：US20120223300A1

公开(公告)日：2012-09-06

申请号：US13172200

申请日：2011-06-29

申请人： Su-Hyoung KANG ,  Yoon Ho KHANG ,  Dong Jo KIM ,  Hyun Jae NA

发明人： Su-Hyoung KANG ,  Yoon Ho KHANG ,  Dong Jo KIM ,  Hyun Jae NA

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L27/1248 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/78606 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

摘要： A thin film transistor array panel and a manufacturing method capable of forming an insulating layer made of different materials for a portion contacting an oxide semiconductor and a second portion without an additional process. The thin film transistor array panel includes: a gate electrode; a source electrode and a drain electrode spaced apart from each other, each of the source and drain electrodes comprising a lower layer and an upper layer; an insulating layer disposed between the gate electrode and the source and drain electrodes; a semiconductor, the source electrode and the drain electrode being electrically connected to the semiconductor; a first passivation layer contacting the lower layer of the source and drain electrodes but not contacting the upper layer of the source and drain electrodes; and a second passivation layer disposed on the upper layer of the source and drain electrodes. The first passivation layer may be made of silicon oxide, and the second passivation may be made of silicon nitride.

摘要翻译： 一种薄膜晶体管阵列面板和能够形成由不同材料制成的绝缘层的制造方法，用于与氧化物半导体和第二部分接触的部分，而不需要额外的工艺。 薄膜晶体管阵列面板包括：栅电极; 源电极和漏电极彼此间隔开，源极和漏极中的每一个包括下层和上层; 绝缘层，设置在所述栅极电极和所述源极和漏极之间; 半导体，源电极和漏极电连接到半导体; 第一钝化层接触源极和漏极的下层，但不接触源极和漏极的上层; 以及设置在源电极和漏电极的上层上的第二钝化层。 第一钝化层可以由氧化硅制成，并且第二钝化可以由氮化硅制成。

公开(公告)号：US20120126233A1

公开(公告)日：2012-05-24

申请号：US13078790

申请日：2011-04-01

申请人： Chong Sup CHANG ,  Yoon Ho KHANG ,  Hyung Jun KIM ,  Se Hwan YU ,  Sang Ho PARK ,  Su-Hyoung KANG ,  Myoung Geun CHA ,  Young Ki SHIN ,  Ji Seon LEE

发明人： Chong Sup CHANG ,  Yoon Ho KHANG ,  Hyung Jun KIM ,  Se Hwan YU ,  Sang Ho PARK ,  Su-Hyoung KANG ,  Myoung Geun CHA ,  Young Ki SHIN ,  Ji Seon LEE

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L27/124 ,  H01L27/1288 ,  H01L29/42384

摘要： Provided is a thin film transistor array panel. A thin film transistor array panel according to an exemplary embodiment includes a gate wire having a first region where the gate line is disposed, and a second region where the gate electrode is disposed, and a thickness of the gate wire formed in the first region is greater than the thickness of the gate wire that is formed in the second region.

摘要翻译： 提供了一种薄膜晶体管阵列面板。 根据示例性实施例的薄膜晶体管阵列面板包括栅极线，栅极线具有设置栅极线的第一区域和设置栅电极的第二区域，并且形成在第一区域中的栅极线的厚度为 大于在第二区域中形成的栅极线的厚度。

公开(公告)号：US20120138920A1

公开(公告)日：2012-06-07

申请号：US13099108

申请日：2011-05-02

申请人： Yoon Ho KHANG ,  Se Hwan YU ,  Chong Sup CHANG ,  Sang Ho PARK ,  Su-Hyoung KANG

发明人： Yoon Ho KHANG ,  Se Hwan YU ,  Chong Sup CHANG ,  Sang Ho PARK ,  Su-Hyoung KANG

IPC分类号： H01L29/12 ,  H01L21/336

CPC分类号： H01L27/1225 ,  H01L29/7869

摘要： A thin film transistor array panel is provided that includes: a gate electrode that is disposed on an insulating substrate; a gate insulating layer that is disposed on the gate electrode; an oxide semiconductor that is disposed on the gate insulating layer; a blocking layer that is disposed on the oxide semiconductor; a source electrode and a drain electrode that are disposed on the blocking layer; a passivation layer that is disposed on the source electrode and drain electrode; and a pixel electrode that is disposed on the passivation layer. The blocking layer includes a first portion that is covered by the source electrode and drain electrode and a second portion that is not covered by the source electrode and drain electrode, and the first portion and the second portion include different materials.

摘要翻译： 提供薄膜晶体管阵列面板，其包括：设置在绝缘基板上的栅电极; 栅极绝缘层，设置在栅电极上; 设置在所述栅极绝缘层上的氧化物半导体; 设置在所述氧化物半导体上的阻挡层; 设置在所述阻挡层上的源电极和漏电极; 钝化层，其设置在所述源电极和所述漏电极上; 以及设置在钝化层上的像素电极。 阻挡层包括由源电极和漏电极覆盖的第一部分和未被源电极和漏电极覆盖的第二部分，并且第一部分和第二部分包括不同的材料。

公开(公告)号：US20100045918A1

公开(公告)日：2010-02-25

申请号：US12495828

申请日：2009-07-01

申请人： Kyoung-Tai HAN ,  Seong-Young LEE ,  Hyang-Shik KONG ,  Se-Hwan YU ,  Byung-Duk YANG ,  Su-Hyoung KANG ,  Kyung-Sook JEON

发明人： Kyoung-Tai HAN ,  Seong-Young LEE ,  Hyang-Shik KONG ,  Se-Hwan YU ,  Byung-Duk YANG ,  Su-Hyoung KANG ,  Kyung-Sook JEON

IPC分类号： G02F1/1345 ,  G02F1/1343 ,  G02F1/13

CPC分类号： G02F1/1345 ,  G02F1/1343 ,  G02F2001/133388

摘要： A liquid crystal display capable of reducing the stray capacitance of a non-display region and a method of manufacturing the same. The liquid crystal display includes a first substrate, gate lines and data lines intersecting each other on the first substrate to define pixels, a second substrate arranged opposite to the first substrate, a common electrode formed in a display area of the second substrate in which an image is displayed, and a floating electrode formed in a non-display region of the second substrate in which no image is displayed.

摘要翻译： 一种能够降低非显示区域的杂散电容的液晶显示器及其制造方法。 液晶显示器包括：第一基板，在第一基板上彼此相交的栅极线和数据线，以限定像素;与第一基板相对布置的第二基板;形成在第二基板的显示区域中的公共电极， 显示图像，以及形成在第二基板的不显示图像的非显示区域中的浮动电极。

公开(公告)号：US20100038648A1

公开(公告)日：2010-02-18

申请号：US12420958

申请日：2009-04-09

申请人： Young-Je CHO ,  Byung-Duk YANG ,  Eun-Guk LEE ,  Sang-Yong NO ,  Hyang-Shik KONG ,  Sung-Hoon KIM ,  Su-Hyoung KANG ,  Sung-Jae MOON ,  Sung-Wook KANG ,  Yeong-Beom LEE

发明人： Young-Je CHO ,  Byung-Duk YANG ,  Eun-Guk LEE ,  Sang-Yong NO ,  Hyang-Shik KONG ,  Sung-Hoon KIM ,  Su-Hyoung KANG ,  Sung-Jae MOON ,  Sung-Wook KANG ,  Yeong-Beom LEE

IPC分类号： H01L33/00

CPC分类号： G02F1/136227 ,  G02F1/13394 ,  G02F1/136209 ,  G02F1/136286 ,  G02F2001/133388 ,  G02F2001/136222 ,  H01L27/1248

摘要： A thin film transistor array panel including a substrate; a display area signal line; a display area thin film transistor; a peripheral area signal line; a black matrix disposed on the display area signal line, the display area thin film transistor, and the peripheral area signal line, the black matrix including a first and a second contact holes exposing the peripheral area signal line; a protrusion member disposed on the peripheral area signal line, the protrusion member overlapping the peripheral area signal line; a transparent connector disposed on the black matrix and within the peripheral area, wherein the transparent connector contacts the peripheral area signal line through at least one of the first and the second contact holes and includes a protrusion within at least one of the first and the second contact holes which corresponds to the protrusion member; and a pixel electrode.

摘要翻译： 一种薄膜晶体管阵列面板，包括基板; 显示区信号线; 显示区薄膜晶体管; 外围区域信号线; 设置在显示区域信号线上的黑色矩阵，显示区域薄膜晶体管和外围区域信号线，黑色矩阵包括暴露外围区域信号线的第一和第二接触孔; 突出部件，配置在所述周边区域信号线上，所述突出部件与所述周边区域信号线重叠; 透明连接器，其设置在所述黑矩阵上并在所述周边区域内，其中所述透明连接器通过所述第一和第二接触孔中的至少一个接触所述外围区域信号线，并且包括在所述第一和第二接触孔中的至少一个内的突起 对应于突出部件的接触孔; 和像素电极。