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    Phosphor
    1.
    发明授权
    Phosphor 失效
    磷

    公开(公告)号：US06531072B1

    公开(公告)日：2003-03-11

    申请号：US09635062

    申请日：2000-08-09

    申请人： Yoriko Suda ,  Kenichi Honda ,  Yoshitaka Sato ,  Hitoshi Toki

    发明人： Yoriko Suda ,  Kenichi Honda ,  Yoshitaka Sato ,  Hitoshi Toki

    IPC分类号： C09K1106

    CPC分类号： C09K11/66 ,  C09K11/62

    摘要： A phosphor in the form of a columnar powder capable of exhibiting enhanced luminous efficiency, providing various luminous colors by electron excitation depending on the selection of elements added thereto and having improved life characteristics. The phosphor is made by heating a starting material constituted by a GaN based phosphor material to a temperature equal to or greater than a sublimation temperature thereof. The phosphor thus obtained is represented by Ga1−xInxN:A,B, wherein x is larger than or equal to 0 and smaller than 1 (0≦x

    摘要翻译： 能够显示增强的发光效率的柱状粉末形式的荧光体，根据添加到其上的元素的选择并通过电子激发提供各种发光颜色并具有改善的寿命特性。 通过将由GaN基荧光体材料构成的原料加热到等于或高于其升华温度的温度来制造荧光体。 由此获得的荧光体由Ga1-xInxN：A，B表示，其中x大于或等于0且小于1（0 <= x <1），A是Zn或Mg，B是Si或Ge。

    WIRELESS IC TAG AND METHOD FOR MANUFACTURING WIRELESS IC TAG
    2.
    发明申请
    WIRELESS IC TAG AND METHOD FOR MANUFACTURING WIRELESS IC TAG 有权
    无线IC标签和制造无线IC标签的方法

    公开(公告)号：US20110006119A1

    公开(公告)日：2011-01-13

    申请号：US12525042

    申请日：2008-05-12

    申请人： Kenichi Honda

    发明人： Kenichi Honda

    IPC分类号： G06K19/077 ,  H01Q1/38

    CPC分类号： G06K19/07749 ,  G06K19/0775 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83192 ,  H01Q1/2225 ,  H01Q7/00 ,  H05K1/165 ,  H05K3/222 ,  H05K3/3421 ,  H05K3/3484 ,  H05K2201/10287 ,  H05K2201/10674 ,  Y10T29/49018 ,  H01L2924/00

    摘要： A wireless IC tag which has an electrically insulative substrate, an antenna circuit provided on the surface of the substrate and an IC chip connected to the antenna circuit, wherein the antenna circuit is formed of solder and the IC chip is connected to the antenna circuit via the solder, andA wireless IC tag comprising an electrically insulative substrate, an antenna circuit provided on the surface of the substrate, an IC chip connected to the antenna circuit, and a jumper wire connected to the antenna circuit, wherein the antenna circuit is formed of a solder, the jumper wire is insulatively coated with a resin composition that evaporates, decomposes, or melts at a temperature not higher than a soldering temperature, and the jumper wire is located on the same side of the substrate where the antenna circuit is provided

    摘要翻译： 具有电绝缘性基板的无线IC标签，设置在基板表面的天线电路和与天线电路连接的IC芯片，其中天线电路由焊料形成，IC芯片经天线电路连接到天线电路 焊料和A无线IC标签，其包括电绝缘基板，设置在基板表面上的天线电路，连接到天线电路的IC芯片和连接到天线电路的跳线，其中形成天线电路 的焊料，在不高于焊接温度的温度下蒸镀，分解或熔化的树脂组合物绝缘地涂覆跳线，并且跨接线位于设置有天线电路的基板的同一侧

    Three-dimensional machining method
    3.
    发明授权
    Three-dimensional machining method 失效
    三维加工方法

    公开(公告)号：US5515290A

    公开(公告)日：1996-05-07

    申请号：US323025

    申请日：1994-10-14

    申请人： Kenichi Honda

    发明人： Kenichi Honda

    IPC分类号： G05B19/4099

    CPC分类号： G05B19/4099 ,  Y02P90/265

    摘要： A plurality of curved surfaces which have distinct characteristics are defined as a unified curved surface. The definition is made by a group of polynomials with respect to parameters u and v in two directions reflecting the characteristics of the curved surfaces. Then, paths of a cutting tool to machine the unified curved surface are generated by using the polynomials. Further, a curved surface is divided by a curve into two regions, and a point is designated in one of the regions. Only with respect to the region which includes the designated point, paths of the cutting tool are generated.

    摘要翻译： 具有不同特征的多个曲面被定义为统一的曲面。 该定义通过反映曲面特征的两个方向上的参数u和v的一组多项式来进行。 然后，通过使用多项式来生成用于加工统一曲面的切削工具的路径。 此外，曲面被曲线分割为两个区域，并且在一个区域中指定点。 仅对于包括指定点的区域，生成切削工具的路径。

    Three-dimensional machining method
    4.
    发明授权
    Three-dimensional machining method 失效
    三维加工方法

    公开(公告)号：US5369592A

    公开(公告)日：1994-11-29

    申请号：US966460

    申请日：1992-10-26

    申请人： Kenichi Honda

    发明人： Kenichi Honda

    IPC分类号： B23Q15/00 ,  G05B19/4097 ,  G05B19/4099 ,  G05B19/41 ,  G05B19/4103 ,  G05B19/4155 ,  G06F15/46 ,  G05B19/403

    CPC分类号： G05B19/41 ,  G05B19/4099 ,  G05B2219/35114 ,  G05B2219/35118

    摘要： A three-dimensional machining method in which paths of the center of a machine tool are calculated from at least one defined curve to machine a surface which is smooth and includes the defined curve. For continuous machining of a first surface and a second surface, the intersection of a tool center path to machine the first surface and the offset surface of the second surface is calculated, and the intersection of a tool center path to machine the second surface and the offset surface of the first surface is calculated. Then, a tool center path to create a connecting surface between the intersections is generated.

    摘要翻译： 一种三维加工方法，其中从至少一个限定的曲线计算机床中心的路径，以加工平滑并包括所述限定曲线的表面。 对于第一表面和第二表面的连续加工，计算刀具中心路径到第二表面的第一表面和偏移表面的加工，并且刀具中心路径与第二表面和 计算第一表面的偏移表面。 然后，产生用于在交点之间创建连接表面的工具中心路径。

    Thyristor with improved dv/dt resistance
    7.
    发明授权
    Thyristor with improved dv/dt resistance 失效
    晶闸管具有改善的dv / dt电阻

    公开(公告)号：US5637886A

    公开(公告)日：1997-06-10

    申请号：US388471

    申请日：1995-02-14

    申请人： Katsumi Satoh ,  Kenichi Honda ,  Kazuhiko Niwayama

    发明人： Katsumi Satoh ,  Kenichi Honda ,  Kazuhiko Niwayama

    IPC分类号： H01L29/74 ,  H01L29/861 ,  H01L31/111

    CPC分类号： H01L29/7428 ,  H01L31/1113

    摘要： When an abrupt voltage noise is applied across an anode electrode (A) and a cathode electrode (K), displacement currents (I.sub.10 to I.sub.30) which are responsive to junction capacitances (C.sub.10 to C.sub.30) of respective unit thyristors (ST.sub.1, ST.sub.2, MT) are generated. The displacement currents (I.sub.10 to I.sub.30) flow into a compensation electrode (C) through paths in a P base layer (2) having resistances (R.sub.10 to R.sub.30), and further flow to an external power source through the cathode electrode (K) which is short-circuited with the compensation electrode (C). The paths of the three displacement currents (I.sub.10 to I.sub.30) are separated from each other by resistances (R.sub.12, R.sub.23). Therefore, a forward bias voltage of a junction (D.sub.10) caused by the displacement current (I.sub.10) is attenuated by the displacement current (I.sub.20), while a forward bias voltage of a junction (D.sub.20) caused by the displacement current (I.sub.20) is attenuated by the displacement current (I.sub.30). Thus, it is possible to improve a thyristor of a multistage structure in dv/dt resistance, at no sacrifice of sensitivity.

    摘要翻译： 当在阳极电极（A）和阴极电极（K）之间施加突然的电压噪声时，响应各单位晶闸管（ST1，ST2，MT）的结电容（C10〜C30）的位移电流（I10〜I30） ）。 位移电流（I10〜I30）通过具有电阻（R10〜R30）的P基极层（2）中的路径流入补偿电极（C），并通过阴极电极（K）进一步流向外部电源 与补偿电极（C）短路。 三个位移电流（I10〜I30）的路径通过电阻（R12，R23）彼此分离。 因此，由位移电流（I10）引起的接点（D10）的正向偏置电压被位移电流（I20）衰减，而由位移电流（I20）引起的接点（D20）的正向偏置电压为 被位移电流衰减（I30）。 因此，可以在不牺牲灵敏度的情况下，以dv / dt电阻改善多级结构的晶闸管。