公开(公告)号：US5637886A

公开(公告)日：1997-06-10

申请号：US388471

申请日：1995-02-14

申请人： Katsumi Satoh ,  Kenichi Honda ,  Kazuhiko Niwayama

发明人： Katsumi Satoh ,  Kenichi Honda ,  Kazuhiko Niwayama

IPC分类号： H01L29/74 ,  H01L29/861 ,  H01L31/111

CPC分类号： H01L29/7428 ,  H01L31/1113

摘要： When an abrupt voltage noise is applied across an anode electrode (A) and a cathode electrode (K), displacement currents (I.sub.10 to I.sub.30) which are responsive to junction capacitances (C.sub.10 to C.sub.30) of respective unit thyristors (ST.sub.1, ST.sub.2, MT) are generated. The displacement currents (I.sub.10 to I.sub.30) flow into a compensation electrode (C) through paths in a P base layer (2) having resistances (R.sub.10 to R.sub.30), and further flow to an external power source through the cathode electrode (K) which is short-circuited with the compensation electrode (C). The paths of the three displacement currents (I.sub.10 to I.sub.30) are separated from each other by resistances (R.sub.12, R.sub.23). Therefore, a forward bias voltage of a junction (D.sub.10) caused by the displacement current (I.sub.10) is attenuated by the displacement current (I.sub.20), while a forward bias voltage of a junction (D.sub.20) caused by the displacement current (I.sub.20) is attenuated by the displacement current (I.sub.30). Thus, it is possible to improve a thyristor of a multistage structure in dv/dt resistance, at no sacrifice of sensitivity.

摘要翻译： 当在阳极电极（A）和阴极电极（K）之间施加突然的电压噪声时，响应各单位晶闸管（ST1，ST2，MT）的结电容（C10〜C30）的位移电流（I10〜I30） ）。 位移电流（I10〜I30）通过具有电阻（R10〜R30）的P基极层（2）中的路径流入补偿电极（C），并通过阴极电极（K）进一步流向外部电源 与补偿电极（C）短路。 三个位移电流（I10〜I30）的路径通过电阻（R12，R23）彼此分离。 因此，由位移电流（I10）引起的接点（D10）的正向偏置电压被位移电流（I20）衰减，而由位移电流（I20）引起的接点（D20）的正向偏置电压为 被位移电流衰减（I30）。 因此，可以在不牺牲灵敏度的情况下，以dv / dt电阻改善多级结构的晶闸管。

公开(公告)号：US5574297A

公开(公告)日：1996-11-12

申请号：US407650

申请日：1995-03-21

申请人： Nozomu Sennenbara ,  Kouji Niinobu ,  Kazuhiko Niwayama ,  Futoshi Tokunoh

发明人： Nozomu Sennenbara ,  Kouji Niinobu ,  Kazuhiko Niwayama ,  Futoshi Tokunoh

IPC分类号： H01L29/74 ,  H01L29/08 ,  H01L29/417 ,  H01L29/744 ,  H01L31/111

CPC分类号： H01L29/744 ,  H01L24/06 ,  H01L29/0834 ,  H01L29/41716 ,  H01L2924/1301

摘要： In order to compatibly implement improvement in withstand voltage and ON-state resistance as well as reduction in turnon loss and improvement in di/dt resistance, an n buffer layer (12) is locally exposed on a lower surface of a semiconductor substrate (160), while a polysilicon additional resistive layer (104) is formed to cover the exposed surface. An anode electrode (101) covering the lower surface of the semiconductor substrate (160) is connected to a p emitter layer (11) and the additional resistive layer (104). Thus, the n buffer layer (12) and the anode electrode (101) are connected with each other through the additional resistive layer (104), whereby a gate trigger current is reduced. Thus, turnon loss is reduced and di/dt resistance is increased. At the same time, the withstand voltage and the ON-state resistance are excellent due to provision of the n buffer layer (12). Thus, the turnon loss is reduced and the di/dt resistance is improved without deteriorating the withstand voltage and the ON-state resistance.

摘要翻译： 为了兼容地实现耐压和导通电阻的改善以及降低漏电损耗和改善di / dt电阻，在半导体衬底（160）的下表面上局部露出n缓冲层（12） ，同时形成多晶硅附加电阻层（104）以覆盖暴露的表面。 覆盖半导体衬底（160）的下表面的阳极电极（101）连接到p发射极层（11）和附加电阻层（104）。 因此，n缓冲层（12）和阳极电极（101）通过附加电阻层（104）彼此连接，从而减小了栅极触发电流。 因此，导通损失减小，di / dt电阻增加。 同时，由于提供n缓冲层（12），耐压和导通电阻极好。 因此，在不降低耐压和导通电阻的情况下，螺线管损耗减小，di / dt电阻提高。

公开(公告)号：US4790620A

公开(公告)日：1988-12-13

申请号：US326252

申请日：1981-12-01

申请人： Kazuhiko Niwayama

发明人： Kazuhiko Niwayama

IPC分类号： G02B6/42 ,  H01L31/02 ,  G02B6/36 ,  H01J5/16 ,  H01L31/12

CPC分类号： G02B6/4212 ,  G02B6/4206 ,  G02B6/4295

摘要： An optical coupling device for coupling an optical fiber to a photo-semiconductor device wherein the light emitting end of the optical fiber is disposed in spaced relation to the light sensitive area of the photo-semiconductor device includes a light transmitting transparent resin completely filling the space between the end of the optical fiber and the light sensitive area of the photo-semiconductor device and a light reflecting resin film completely covering the exposed surface of the transparent resin.

摘要翻译： 一种用于将光纤耦合到光电半导体器件的光耦合器件，其中光纤的发光端以与光半导体器件的光敏区域间隔的关系设置，包括完全填充空间的透光透明树脂 在光纤的端部与光电半导体器件的光敏区域之间，以及完全覆盖透明树脂的暴露表面的光反射树脂膜。

公开(公告)号：US5428229A

公开(公告)日：1995-06-27

申请号：US323697

申请日：1994-10-18

申请人： Kazuhiko Niwayama ,  Futoshi Tokunou

发明人： Kazuhiko Niwayama ,  Futoshi Tokunou

IPC分类号： H01L29/78 ,  H01L21/331 ,  H01L21/336 ,  H01L23/48 ,  H01L29/06 ,  H01L29/739 ,  H01L29/10

CPC分类号： H01L29/66333 ,  H01L24/72 ,  H01L29/66348 ,  H01L29/7397 ,  H01L2224/45124 ,  H01L24/45 ,  H01L29/0657 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01051 ,  H01L2924/12036 ,  H01L2924/1301 ,  H01L2924/13091 ,  H01L2924/30105

摘要： A MOS semiconductor device which exhibits high switching operations including high turn-on and an excellent self-cooling capability. The device prevents damage to insulation films and electrodes thereof. An IGT includes a multi-layer structure having a p type emitter layer, an n type base layer, a p type base layer and an n type emitter layer superimposed therein. A gate electrode and an overlying gate oxide film are disposed on a recessed surface of the multi-layer structure. A cathode electrode is located only in and around a cathode surface so that most of the top surface of the gate electrode is uncovered. Via an intervening cathode distortion snubbering plate, the cathode electrode is in pressure contact with a cathode electrode body. The gate and the cathode electrodes have a reduced capacitance therebetween. The cathode electrode body serves to cool the cathode electrode. The gate electrode and the gate oxide film are protected from stress, and hence, will not be damaged by stress.

摘要翻译： 表现出高开关操作的MOS半导体器件，其具有高导通和优异的自冷能力。 该装置可防止对绝缘膜及其电极的损坏。 IGT包括具有p型发射极层，n型基极层，p型基极层和叠置在其中的n型发射极层的多层结构。 栅电极和覆盖栅氧化膜设置在多层结构的凹陷表面上。 阴极仅位于阴极表面中并且位于阴极表面周围，使得栅电极的顶表面的大部分未被覆盖。 通过中间的阴极失真缓冲板，阴极电极与阴极电极体压力接触。 栅极和阴极之间的电容减小。 阴极电极体用于冷却阴极电极。 保护栅电极和栅极氧化膜免受应力，因此不会受到应力的损害。

公开(公告)号：US5346859A

公开(公告)日：1994-09-13

申请号：US125836

申请日：1993-09-24

申请人： Kazuhiko Niwayama

发明人： Kazuhiko Niwayama

IPC分类号： H01L23/00 ,  H01L23/051 ,  H01L23/48 ,  H01L21/60

CPC分类号： H01L24/72 ,  H01L23/051 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/12036 ,  H01L2924/1301 ,  H01L2924/351 ,  Y10T29/49169

摘要： Coned disc springs (84, 86) lie between a gate extracting electrode (80G) held in a ringlike recess (63) of an external cathode electrode (60K) and a bottom surface of the ringlike recess (63). A semiconductor body (30) is pressed against an anode distortion buffering plate (50A) by a urging force of the coned disc springs (84, 86) for vertical positional fixation of the semiconductor body (30). This enables the semiconductor body to be prevented from damages and deformation in a full press-pack type semiconductor device.

摘要翻译： 圆盘弹簧（84,86）位于保持在外部阴极电极（60K）的环形凹部（63）中的栅极引出电极（80G）和环状凹部（63）的底面之间。 通过用于半导体本体（30）的垂直定位的碟形弹簧（84,86）的推动力将半导体本体（30）压靠阳极变形缓冲板（50A）。 这使得可以防止半导体本体在全压模包装型半导体器件中的损坏和变形。

公开(公告)号：US5345095A

公开(公告)日：1994-09-06

申请号：US12464

申请日：1993-02-02

申请人： Kazuhiko Niwayama

发明人： Kazuhiko Niwayama

IPC分类号： H01L29/74 ,  H01L21/332 ,  H01L29/08 ,  H01L29/745 ,  H01L29/749 ,  H01L31/111

CPC分类号： H01L29/0839 ,  H01L29/7455

摘要： A self arc-extinguishing thyristor having a large main current is disclosed. An n-type base layer is formed on a p-type anode layer. The n-type base layer includes in its top center portion a relatively heavily doped p+-type region which is surrounded by p-type region. A p-type base layer is locally coated at its top surface with a relatively thin first n-type emitter layer and a relatively thick second n-type emitter layer. A gate electrode buried in a gate oxide film is disposed on two channel regions and areas around the same. This structure suppresses a current amplification factor of a parasitic thyristor which is formed by the n-type base layer, the p-type region and the first n-type emitter layer, which in turn represses latching up of the parasitic thyristor.

摘要翻译： 公开了一种具有大的主电流的自灭弧晶闸管。 n型基层形成在p型阳极层上。 n型基层在其顶部中间部分包括被p型区域包围的相对重掺杂的p +型区域。 p型基层在其顶表面局部涂覆有较薄的第一n型发射极层和较厚的第二n型发射极层。 埋在栅极氧化物膜中的栅电极设置在两个沟道区域和周围的区域上。 该结构抑制由n型基极层，p型区域和第一n型发射极层形成的寄生晶闸管的电流放大系数，这进而抑制寄生晶闸管的锁存。

公开(公告)号：US4881118A

公开(公告)日：1989-11-14

申请号：US346277

申请日：1989-04-28

申请人： Kazuhiko Niwayama ,  Tsutomu Nakagawa ,  Futoshi Tokunoh ,  Shigekazu Yoshida

发明人： Kazuhiko Niwayama ,  Tsutomu Nakagawa ,  Futoshi Tokunoh ,  Shigekazu Yoshida

IPC分类号： H01L23/051 ,  H01L23/492

CPC分类号： H01L23/051 ,  H01L23/492 ,  H01L2924/0002

摘要： One surface of a cathode sliding compensator is finished as an irregular surface while another surface thereof is finished as a sliding surface. The irregular surface is arranged to contact with a cathode electrode layer of a semiconductor element while the sliding surface is arranged to contact with a cathode conductor, and junction surfaces therebetween are electrically and mechanically connected by pressurization. Thus, the irregular surface bites into the cathode electrode layer to attain excellent electrical and mechanical connection between the cathode electrode layer and the cathode sliding compensator, while slidingness can be effectively retained between the cathode conductor and the cathode sliding compensator by the function of the sliding surface.

摘要翻译： 阴极滑动补偿器的一个表面被完成为不规则表面，而其另一表面被完成为滑动表面。 不规则表面布置成与半导体元件的阴极电极层接触，同时滑动表面设置成与阴极导体接触，并且其间的接合表面通过加压电连接和机械连接。 因此，不规则表面咬入阴极电极层，以在阴极电极层和阴极滑动补偿器之间获得优良的电气和机械连接，同时通过滑动的功能可以有效地保持阴极导体和阴极滑动补偿器之间的滑动性 表面。

公开(公告)号：US4797727A

公开(公告)日：1989-01-10

申请号：US521510

申请日：1983-08-08

申请人： Kazuhiko Niwayama

发明人： Kazuhiko Niwayama

IPC分类号： H01L21/52 ,  H01L23/051 ,  H01L29/74 ,  H01L31/111 ,  H01L23/42 ,  H01L23/44 ,  H01L23/46

CPC分类号： H01L29/74 ,  H01L23/051 ,  H01L31/1113 ,  H01L2924/0002 ,  Y10S257/926

摘要： A thyristor comprising a thyristor element with a trigger section 1a formed on the surface thereof. The thyristor element is attached to a metal disk 2 having at least three faces 2a on its periphery which are all a common distance l from the center of the trigger section. One electrode unit 4 is attached to the opposing surface of the metal disk and a second electrode unit 3 is attached to the opposing surface of the thyristor element. A trigger signal guide 10 penetrates an insulating tube 5 surrounding the element and one end of the guide is positioned on the central axis of the insulating tube. Positioning members 11 of equal width are compressively inserted between the insulating tube and the faces of the metal disk.

摘要翻译： 一种晶闸管，包括在其表面上形成有触发器部分1a的晶闸管元件。 晶闸管元件附接到金属盘2，金属盘2在其周边上具有至少三个面2a，它们都与触发器部分的中心相距一般的距离l。 一个电极单元4附接到金属盘的相对表面，并且第二电极单元3附接到晶闸管元件的相对表面。 触发信号引导件10穿过围绕元件的绝缘管5，并且引导件的一端位于绝缘管的中心轴线上。 相等宽度的定位构件11被压缩地插入绝缘管和金属盘的表面之间。

公开(公告)号：US5278434A

公开(公告)日：1994-01-11

申请号：US888656

申请日：1992-05-27

申请人： Kazuhiko Niwayama

发明人： Kazuhiko Niwayama

IPC分类号： H01L23/00 ,  H01L23/051 ,  H01L23/48 ,  H01L23/02

CPC分类号： H01L24/72 ,  H01L23/051 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/12036 ,  H01L2924/1301 ,  H01L2924/351 ,  Y10T29/49169

摘要： Coned disc springs (84, 86) lie between a gate extracting electrode (80G) held in a ringlike recess (63) of an external cathode electrode (60K) and a bottom surface of the ringlike recess (63). A semiconductor body (30) is pressed against an anode distortion buffering plate (50A) by a urging force of the coned disc springs (84, 86) for vertical positional fixation of the semiconductor body (30). This enables the semiconductor body to be prevented from damages and deformation in a full press-pack type semiconductor device.

摘要翻译： 圆盘弹簧（84,86）位于保持在外部阴极电极（60K）的环形凹部（63）中的栅极引出电极（80G）和环状凹部（63）的底面之间。 通过用于半导体本体（30）的垂直定位的碟形弹簧（84,86）的推动力将半导体本体（30）压靠阳极变形缓冲板（50A）。 这使得可以防止半导体本体在全压模包装型半导体器件中的损坏和变形。

公开(公告)号：US5121189A

公开(公告)日：1992-06-09

申请号：US605277

申请日：1990-10-30

申请人： Kazuhiko Niwayama

发明人： Kazuhiko Niwayama

IPC分类号： H01L29/744 ,  H01L23/051 ,  H01L29/74

CPC分类号： H01L23/051 ,  H01L2924/0002

摘要： A flat-pack type semiconductor device has an anode buffer plate (50) on a semiconductor element (1). The anode buffer plate consists of a central position (51) and a plurality of arms (61, 63) extending therefrom. Each of the arms has a straight portion (61a) placed on a guide ring (70) and a hooked-portion (61b) inserted in the gap (73) between the guide ring and an insulating cylinder (10).