公开(公告)号：US20140092542A1

公开(公告)日：2014-04-03

申请号：US13630894

申请日：2012-09-28

申请人： Yoshifumi NISHI ,  Mark MACDONALD

发明人： Yoshifumi NISHI ,  Mark MACDONALD

IPC分类号： G06F1/20 ,  H05K7/20

CPC分类号： G06F1/1616 ,  G06F1/203

摘要： An electronic device is provided that includes a base having a top portion and a bottom portion. The bottom portion may include a first bottom part and a second bottom part. The first bottom part may form a first plane, and the second bottom part may form a second plane, the second plane being non-planar with the first plane. The second bottom part may include an input opening. The top portion of the base may include an output opening. The input opening and the output opening may allow air to flow from behind the electronic device to over the base.

摘要翻译： 提供一种电子装置，其包括具有顶部和底部的基部。 底部可包括第一底部和第二底部。 第一底部可以形成第一平面，并且第二底部可以形成第二平面，第二平面与第一平面非平面。 第二底部可以包括输入开口。 基座的顶部可包括输出开口。 输入开口和输出开口可允许空气从电子设备后面流过基座。

公开(公告)号：US20140092544A1

公开(公告)日：2014-04-03

申请号：US13630947

申请日：2012-09-28

申请人： Yoshifumi NISHI ,  Mark MacDonald ,  Douglas Heymann

发明人： Yoshifumi NISHI ,  Mark MacDonald ,  Douglas Heymann

IPC分类号： G06F1/20 ,  G06F1/16

CPC分类号： G06F1/1616 ,  G06F1/203

摘要： An electronic device is provided that includes a base having a first side and a second side, and a lid having a first side and a second side. The electronic device may also include a heat exchanger provided at the base. The heat exchanger may have a first surface exposed to outside the base.

摘要翻译： 提供了一种电子设备，其包括具有第一侧和第二侧的基座，以及具有第一侧和第二侧的盖。 电子设备还可以包括设置在基座处的热交换器。 热交换器可以具有暴露于基部外部的第一表面。

公开(公告)号：US20090152652A1

公开(公告)日：2009-06-18

申请号：US12323770

申请日：2008-11-26

申请人： Yoshifumi NISHI ,  Yoshinori Tsuchiya ,  Takashi Yamauchi ,  Junji Koga

发明人： Yoshifumi NISHI ,  Yoshinori Tsuchiya ,  Takashi Yamauchi ,  Junji Koga

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/4975 ,  H01L21/26506 ,  H01L21/28097 ,  H01L21/28518 ,  H01L21/28537 ,  H01L21/324 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L23/485 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： Described herein is a method of manufacturing a semiconductor device realizing higher performance by reducing contact resistance of an electrode. In the method, a gate insulating film, a gate electrode are formed on a semiconductor substrate. A first metal is deposited substrate, and a metal semiconductor compound layer is formed on the surface of the semiconductor substrate by making the first metal and the semiconductor substrate react each other by a first heat treatment. Ions having a mass equal to or larger than atomic weight of Si are implanted into the metal semiconductor compound layer. A second metal is deposited on the metal semiconductor compound layer. An interface layer is formed by making the second metal segregated at an interface between the metal semiconductor compound layer and the semiconductor substrate by diffusing the second metal through the metal semiconductor compound layer by a second heat treatment.

摘要翻译： 这里描述的是通过降低电极的接触电阻来制造实现更高性能的半导体器件的方法。 在该方法中，在半导体衬底上形成栅极绝缘膜，栅电极。 第一金属是沉积衬底，并且通过使第一金属和半导体衬底通过第一热处理而彼此反应，在半导体衬底的表面上形成金属半导体化合物层。 将具有等于或大于Si原子量的质量的离子注入到金属半导体化合物层中。 第二金属沉积在金属半导体化合物层上。 通过使第二金属通过第二热处理使金属半导体化合物层扩散而使第二金属在金属半导体化合物层和半导体基板之间的界面分离而形成界面层。

公开(公告)号：US20130037776A1

公开(公告)日：2013-02-14

申请号：US13425687

申请日：2012-03-21

申请人： Yoshifumi NISHI ,  Hidenori MIYAGAWA ,  Daisuke MATSUSHITA ,  Jun FUJIKI ,  Takeshi IMAMURA

发明人： Yoshifumi NISHI ,  Hidenori MIYAGAWA ,  Daisuke MATSUSHITA ,  Jun FUJIKI ,  Takeshi IMAMURA

IPC分类号： H01L45/00

CPC分类号： H01L45/085 ,  H01L27/2472 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/148 ,  H01L45/149

摘要： A variable resistance memory according to an embodiment includes: a first wiring; a second wiring intersecting with the first wiring; a first electrode provided in an intersection region between the first wiring and the second wiring, the first electrode being connected to the first wiring; a second electrode connected to the second wiring, the second electrode facing to the first electrode; a variable resistance layer provided between the first electrode and the second electrode; and one of a first insulating layer and a first semiconductor layer formed at side portions of the second electrode. The one of the first insulating layer and the first semiconductor layer, and the second electrode form voids at the side portions of the second electrode.

摘要翻译： 根据实施例的可变电阻存储器包括：第一布线; 与第一布线相交的第二布线; 设置在所述第一布线和所述第二布线之间的交叉区域中的第一电极，所述第一电极连接到所述第一布线; 连接到第二布线的第二电极，第二电极面对第一电极; 设置在所述第一电极和所述第二电极之间的可变电阻层; 以及形成在第二电极的侧部的第一绝缘层和第一半导体层中的一个。 第一绝缘层和第一半导体层中的一个，第二电极形状在第二电极的侧部空隙。

公开(公告)号：US20130077397A1

公开(公告)日：2013-03-28

申请号：US13480853

申请日：2012-05-25

申请人： Takahiro KURITA ,  Yoshifumi NISHI ,  Kosuke TATSUMURA ,  Atsuhiro KINOSHITA

发明人： Takahiro KURITA ,  Yoshifumi NISHI ,  Kosuke TATSUMURA ,  Atsuhiro KINOSHITA

IPC分类号： H01L27/105 ,  G11C11/40

CPC分类号： H01L21/28291 ,  G11C7/02 ,  G11C11/403 ,  H01L21/28282 ,  H01L27/108 ,  H01L27/10873 ,  H01L29/4234 ,  H01L29/516

摘要： A semiconductor device according to an embodiment includes: a first transistor including a gate connected to a first interconnection, a first source, and a first drain, one of the first source and the first drain being connected to a second interconnection; and a second transistor including a gate structure, a second source, and a second drain, one of the second source and second drain being connected to a third interconnection and the other of the second source and second drain being connected to a fourth interconnection. The gate structure includes a gate insulation film, a gate electrode, and a threshold-modulating film provided between the gate insulation film and the gate electrode to modulate a threshold voltage, the other of the first source and first drain of the first transistor is connected to the gate electrode.

摘要翻译： 根据实施例的半导体器件包括：第一晶体管，包括连接到第一互连的栅极，第一源极和第一漏极，第一源极和第一漏极中的一个连接到第二互连; 以及第二晶体管，其包括栅极结构，第二源极和第二漏极，所述第二源极和第二漏极中的一个连接到第三互连，并且所述第二源极和第二漏极中的另一个连接到第四互连。 栅极结构包括栅极绝缘膜，栅极电极和设置在栅极绝缘膜和栅电极之间以调节阈值电压的阈值调制膜，第一晶体管的第一源极和第一漏极中的另一个被连接 到栅电极。

公开(公告)号：US20120243336A1

公开(公告)日：2012-09-27

申请号：US13240087

申请日：2011-09-22

申请人： Yoshifumi NISHI ,  Daisuke HAGISHIMA ,  Shinichi YASUDA ,  Tetsufumi TANAMOTO ,  Takahiro KURITA ,  Atsuhiro KINOSHITA ,  Shinobu FUJITA

发明人： Yoshifumi NISHI ,  Daisuke HAGISHIMA ,  Shinichi YASUDA ,  Tetsufumi TANAMOTO ,  Takahiro KURITA ,  Atsuhiro KINOSHITA ,  Shinobu FUJITA

IPC分类号： G11C16/10 ,  H01L29/792

CPC分类号： H01L27/11568 ,  G11C16/0458 ,  G11C16/10 ,  H01L27/11573 ,  H01L27/11803

摘要： An aspect of the present embodiment, there is provided a nonvolatile programmable logic switch including a first memory cell transistor, a second memory cell transistor, a pass transistor and a first substrate electrode applying a substrate voltage to the pass transistor, wherein a writing voltage is applied to the first wiring, a first voltage is applied to one of a second wiring and a third wiring and a second voltage which is lower than the first voltage is applied to the other of the second wiring and the third wiring, and the first substrate voltage which is higher than the second voltage and lower than the first voltage is applied to a well of the pass transistor, when data is written into the first memory cell transistor or the second memory cell transistor.

摘要翻译： 本实施例的一个方面提供了一种非易失性可编程逻辑开关，包括第一存储单元晶体管，第二存储单元晶体管，传输晶体管和向该通过晶体管施加衬底电压的第一衬底电极，其中写入电压为 施加到第一布线，第一电压施加到第二布线和第三布线中的一个，并且低于第一电压的第二电压施加到第二布线和第三布线中的另一布线，第一基板 当数据被写入第一存储单元晶体管或第二存储单元晶体管时，高于第二电压并低于第一电压的电压被施加到传输晶体管的阱。

公开(公告)号：US20120080739A1

公开(公告)日：2012-04-05

申请号：US13221292

申请日：2011-08-30

申请人： Daisuke HAGISHIMA ,  Atsuhiro KINOSHITA ,  Kazuya MATSUZAWA ,  Kazutaka IKEGAMI ,  Yoshifumi NISHI

发明人： Daisuke HAGISHIMA ,  Atsuhiro KINOSHITA ,  Kazuya MATSUZAWA ,  Kazutaka IKEGAMI ,  Yoshifumi NISHI

IPC分类号： H01L29/792

CPC分类号： H01L29/7881 ,  G11C16/0408 ,  H01L27/1052 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11807 ,  H01L29/66825

摘要： A nonvolatile programmable logic switch according to an embodiment includes: a memory cell transistor including: a first source region and a first drain region of a second conductivity type formed at a distance from each other in a first semiconductor region of a first conductivity type; a first insulating film, a charge storage film, a second insulating film, and a control gate stacked in this order and formed on the first semiconductor region between the first source region and the first drain region; a pass transistor including: a second source region and a second drain region of a second conductivity type formed at a distance from each other in a second semiconductor region of the first conductivity type; a third insulating film, a gate electrode stacked in this order and formed on the second semiconductor region between the second source region and the second drain region, the gate electrode being electrically connected to the first drain region; and an electrode for applying a substrate bias to the first and second semiconductor regions.

摘要翻译： 根据实施例的非易失性可编程逻辑开关包括：存储单元晶体管，包括：在第一导电类型的第一半导体区域中彼此间隔开形成的第二导电类型的第一源极区域和第一漏极区域; 第一绝缘膜，电荷存储膜，第二绝缘膜和控制栅极，并且形成在第一源极区域和第一漏极区域之间的第一半导体区域上; 传输晶体管，包括：在第一导电类型的第二半导体区域中彼此成一定距离地形成的第二导电类型的第二源极区域和第二漏极区域; 第三绝缘膜，栅极电极，并且形成在第二源极区域和第二漏极区域之间的第二半导体区域上，栅极电连接到第一漏极区域; 以及用于将衬底偏压施加到第一和第二半导体区域的电极。

公开(公告)号：US20140070160A1

公开(公告)日：2014-03-13

申请号：US13714946

申请日：2012-12-14

申请人： Takayuki ISHIKAWA ,  Yoshifumi NISHI ,  Shosuke FUJII

发明人： Takayuki ISHIKAWA ,  Yoshifumi NISHI ,  Shosuke FUJII

IPC分类号： H01L45/00

CPC分类号： H01L45/14 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/148 ,  H01L45/165 ,  H01L45/1658

摘要： According to one embodiment, a nonvolatile memory device includes a first electrode, a second electrode, a variable resistance layer. The variable resistance layer is provided between the first electrode and the second electrode. The variable resistance layer contains impurity of a nonmetallic element. The impurity is at least one selected from the group consisting of S, Se, Te, F, Cl, Br, and I.

摘要翻译： 根据一个实施例，非易失性存储器件包括第一电极，第二电极，可变电阻层。 可变电阻层设置在第一电极和第二电极之间。 可变电阻层含有非金属元素的杂质。 杂质是选自S，Se，Te，F，Cl，Br和I中的至少一种。

公开(公告)号：US20100109099A1

公开(公告)日：2010-05-06

申请号：US12609805

申请日：2009-10-30

申请人： Yoshifumi NISHI ,  Atsuhiro Kinoshita

发明人： Yoshifumi NISHI ,  Atsuhiro Kinoshita

IPC分类号： H01L29/78 ,  H01L29/417 ,  H01L21/22 ,  H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/265 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/28537 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/095 ,  H01L29/66507 ,  H01L29/7833

摘要： A semiconductor device including a semiconductor substrate, an interface layer formed on the semiconductor substrate including at least 1×1020 atoms/cm3 of S (Sulfur), a metal-semiconductor compound layer formed on the interface layer, the metal-semiconductor compound layer including at least 1×1020 atoms/cm3 of S in the its whole depth, and a metal electrode formed on the metal-semiconductor compound layer.

摘要翻译： 一种半导体器件，包括半导体衬底，形成在所述半导体衬底上的界面层，所述界面层至少包含1×1020原子/ cm3的S（硫），在所述界面层上形成的金属 - 半导体化合物层，所述金属 - 半导体化合物层包括 在整个深度上至少为1×1020原子/ cm3的S，以及形成在金属 - 半导体化合物层上的金属电极。