公开(公告)号：US20120243336A1

公开(公告)日：2012-09-27

申请号：US13240087

申请日：2011-09-22

申请人： Yoshifumi NISHI ,  Daisuke HAGISHIMA ,  Shinichi YASUDA ,  Tetsufumi TANAMOTO ,  Takahiro KURITA ,  Atsuhiro KINOSHITA ,  Shinobu FUJITA

发明人： Yoshifumi NISHI ,  Daisuke HAGISHIMA ,  Shinichi YASUDA ,  Tetsufumi TANAMOTO ,  Takahiro KURITA ,  Atsuhiro KINOSHITA ,  Shinobu FUJITA

IPC分类号： G11C16/10 ,  H01L29/792

CPC分类号： H01L27/11568 ,  G11C16/0458 ,  G11C16/10 ,  H01L27/11573 ,  H01L27/11803

摘要： An aspect of the present embodiment, there is provided a nonvolatile programmable logic switch including a first memory cell transistor, a second memory cell transistor, a pass transistor and a first substrate electrode applying a substrate voltage to the pass transistor, wherein a writing voltage is applied to the first wiring, a first voltage is applied to one of a second wiring and a third wiring and a second voltage which is lower than the first voltage is applied to the other of the second wiring and the third wiring, and the first substrate voltage which is higher than the second voltage and lower than the first voltage is applied to a well of the pass transistor, when data is written into the first memory cell transistor or the second memory cell transistor.

摘要翻译： 本实施例的一个方面提供了一种非易失性可编程逻辑开关，包括第一存储单元晶体管，第二存储单元晶体管，传输晶体管和向该通过晶体管施加衬底电压的第一衬底电极，其中写入电压为 施加到第一布线，第一电压施加到第二布线和第三布线中的一个，并且低于第一电压的第二电压施加到第二布线和第三布线中的另一布线，第一基板 当数据被写入第一存储单元晶体管或第二存储单元晶体管时，高于第二电压并低于第一电压的电压被施加到传输晶体管的阱。

公开(公告)号：US20120080739A1

公开(公告)日：2012-04-05

申请号：US13221292

申请日：2011-08-30

申请人： Daisuke HAGISHIMA ,  Atsuhiro KINOSHITA ,  Kazuya MATSUZAWA ,  Kazutaka IKEGAMI ,  Yoshifumi NISHI

发明人： Daisuke HAGISHIMA ,  Atsuhiro KINOSHITA ,  Kazuya MATSUZAWA ,  Kazutaka IKEGAMI ,  Yoshifumi NISHI

IPC分类号： H01L29/792

CPC分类号： H01L29/7881 ,  G11C16/0408 ,  H01L27/1052 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11807 ,  H01L29/66825

摘要： A nonvolatile programmable logic switch according to an embodiment includes: a memory cell transistor including: a first source region and a first drain region of a second conductivity type formed at a distance from each other in a first semiconductor region of a first conductivity type; a first insulating film, a charge storage film, a second insulating film, and a control gate stacked in this order and formed on the first semiconductor region between the first source region and the first drain region; a pass transistor including: a second source region and a second drain region of a second conductivity type formed at a distance from each other in a second semiconductor region of the first conductivity type; a third insulating film, a gate electrode stacked in this order and formed on the second semiconductor region between the second source region and the second drain region, the gate electrode being electrically connected to the first drain region; and an electrode for applying a substrate bias to the first and second semiconductor regions.

摘要翻译： 根据实施例的非易失性可编程逻辑开关包括：存储单元晶体管，包括：在第一导电类型的第一半导体区域中彼此间隔开形成的第二导电类型的第一源极区域和第一漏极区域; 第一绝缘膜，电荷存储膜，第二绝缘膜和控制栅极，并且形成在第一源极区域和第一漏极区域之间的第一半导体区域上; 传输晶体管，包括：在第一导电类型的第二半导体区域中彼此成一定距离地形成的第二导电类型的第二源极区域和第二漏极区域; 第三绝缘膜，栅极电极，并且形成在第二源极区域和第二漏极区域之间的第二半导体区域上，栅极电连接到第一漏极区域; 以及用于将衬底偏压施加到第一和第二半导体区域的电极。

公开(公告)号：US20130077397A1

公开(公告)日：2013-03-28

申请号：US13480853

申请日：2012-05-25

申请人： Takahiro KURITA ,  Yoshifumi NISHI ,  Kosuke TATSUMURA ,  Atsuhiro KINOSHITA

发明人： Takahiro KURITA ,  Yoshifumi NISHI ,  Kosuke TATSUMURA ,  Atsuhiro KINOSHITA

IPC分类号： H01L27/105 ,  G11C11/40

CPC分类号： H01L21/28291 ,  G11C7/02 ,  G11C11/403 ,  H01L21/28282 ,  H01L27/108 ,  H01L27/10873 ,  H01L29/4234 ,  H01L29/516

摘要： A semiconductor device according to an embodiment includes: a first transistor including a gate connected to a first interconnection, a first source, and a first drain, one of the first source and the first drain being connected to a second interconnection; and a second transistor including a gate structure, a second source, and a second drain, one of the second source and second drain being connected to a third interconnection and the other of the second source and second drain being connected to a fourth interconnection. The gate structure includes a gate insulation film, a gate electrode, and a threshold-modulating film provided between the gate insulation film and the gate electrode to modulate a threshold voltage, the other of the first source and first drain of the first transistor is connected to the gate electrode.

摘要翻译： 根据实施例的半导体器件包括：第一晶体管，包括连接到第一互连的栅极，第一源极和第一漏极，第一源极和第一漏极中的一个连接到第二互连; 以及第二晶体管，其包括栅极结构，第二源极和第二漏极，所述第二源极和第二漏极中的一个连接到第三互连，并且所述第二源极和第二漏极中的另一个连接到第四互连。 栅极结构包括栅极绝缘膜，栅极电极和设置在栅极绝缘膜和栅电极之间以调节阈值电压的阈值调制膜，第一晶体管的第一源极和第一漏极中的另一个被连接 到栅电极。

公开(公告)号：US20090250742A1

公开(公告)日：2009-10-08

申请号：US12043193

申请日：2008-03-06

申请人： Atsuhiro KINOSHITA ,  Yoshifumi Nishi

发明人： Atsuhiro KINOSHITA ,  Yoshifumi Nishi

IPC分类号： H01L29/788

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/785

摘要： A neuron device includes: a semiconductor layer; source and drain regions formed in the semiconductor layer at a distance from each other; a protection film formed on an upper face of the semiconductor layer; a channel region formed in the semiconductor layer between the source region and the drain region; a pair of gate insulating films formed on two side faces of the channel region; a floating gate electrode including: a first portion covered on the gate insulating films and the protection film; a second portion connected to the first portion; and a third portion provided on the substrate so as to connect to the end portion of the second portion on the opposite side from the first portion; an interelectrode insulating film provided on the first to third portions; and a plurality of control gate electrodes provided on the third portion.

摘要翻译： 神经元装置包括：半导体层; 源极和漏极区域形成在半导体层中彼此间隔一定距离; 形成在所述半导体层的上表面上的保护膜; 在所述源极区域和所述漏极区域之间的所述半导体层中形成的沟道区域; 形成在沟道区域的两个侧面上的一对栅极绝缘膜; 一种浮栅电极，包括：覆盖在栅极绝缘膜和保护膜上的第一部分; 连接到第一部分的第二部分; 以及第三部分，设置在所述基板上，以便在与所述第一部分相反的一侧连接到所述第二部分的端部; 设置在所述第一至第三部分上的电极间绝缘膜; 以及设置在第三部分上的多个控制栅电极。

公开(公告)号：US20080315183A1

公开(公告)日：2008-12-25

申请号：US12052229

申请日：2008-03-20

申请人： Atsuhiro KINOSHITA ,  Yoshifumi Nishi ,  Ken Uchida ,  Junji Koga

发明人： Atsuhiro KINOSHITA ,  Yoshifumi Nishi ,  Ken Uchida ,  Junji Koga

IPC分类号： H01L29/12 ,  H01L21/336

CPC分类号： H01L51/105 ,  B82Y10/00 ,  H01L51/0048 ,  H01L51/0512 ,  H01L51/0541 ,  H01L51/0545

摘要： A high-performance semiconductor device having a channel region structured from a carbon nanotube (CNT) for reducing or minimizing a drain leakage current is provided. This semiconductor device includes, in addition to the CNT-formed channel region, a gate electrode formed to overlie the channel region with a gate insulation film sandwiched therebetween, and a pair of source and drain regions interposing the channel region therebetween. The source and drain regions have portions in contact with the channel region, which portions are made of a specific semiconductor material that is wider in energy band gap than the channel region.

摘要翻译： 提供了一种具有由碳纳米管（CNT）构成的沟道区，用于降低或最小化漏极漏电流的高性能半导体器件。 除了CNT形成的沟道区域之外，该半导体器件还包括形成为覆盖沟道区域的栅电极，其间夹有栅极绝缘膜，并且在其间插入沟道区域的一对源极和漏极区域。 源极区和漏极区具有与沟道区接触的部分，这些部分由能量带隙比通道区宽的特定半导体材料制成。

公开(公告)号：US20140035618A1

公开(公告)日：2014-02-06

申请号：US13613701

申请日：2012-09-13

申请人： Kosuke TATSUMURA ,  Masato ODA ,  Atsuhiro KINOSHITA ,  Koichiro ZAITSU ,  Mari MATSUMOTO ,  Shinichi YASUDA

发明人： Kosuke TATSUMURA ,  Masato ODA ,  Atsuhiro KINOSHITA ,  Koichiro ZAITSU ,  Mari MATSUMOTO ,  Shinichi YASUDA

IPC分类号： H03K19/177

CPC分类号： H03K19/17728 ,  G11C15/04 ,  G11C15/046 ,  H03K19/17712

摘要： A circuit according to embodiments includes: a plurality of bit-string comparators each of which includes a plurality of single-bit comparators each of which includes first and second input terminals, first and second match-determination terminals, and a memory storing data and inverted data in a pair, the first input terminal being connected to a respective search line, the second input terminal being connected to an inverted search line being paired with the respective search line, and a matching line connecting the first and second match-determination terminals of the single-bit comparators; a pre-charge transistor of which source is connected to a supply voltage line; a common matching line connected to a drain of the pre-charge transistor and the matching lines of the bit-string comparators; and an output inverter of which input is connected to the common matching line.

摘要翻译： 根据实施例的电路包括：多个比特串比较器，每个比特串包括多个单比特比较器，每个单比特比较器包括第一和第二输入端，第一和第二匹配确定终端，以及存储数据并反转的存储器 成对的数据，第一输入端子连接到相应的搜索线，第二输入端子连接到与相应搜索线配对的反向搜索线，以及匹配线，连接第一和第二匹配确定端子 单比特比较器; 其源极连接到电源电压线的预充电晶体管; 连接到预充电晶体管的漏极和位串比较器的匹配线的公共匹配线; 以及输入反相器，其输入连接到公共匹配线。

公开(公告)号：US20130181184A1

公开(公告)日：2013-07-18

申请号：US13547567

申请日：2012-07-12

申请人： Kiwamu SAKUMA ,  Masahiro KIYOTOSHI ,  Atsuhiro KINOSHITA ,  Haruka KUSAI

发明人： Kiwamu SAKUMA ,  Masahiro KIYOTOSHI ,  Atsuhiro KINOSHITA ,  Haruka KUSAI

IPC分类号： H01L27/24 ,  H01L21/8234

CPC分类号： H01L45/1233 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/1211 ,  H01L27/222 ,  H01L27/2454 ,  H01L27/2481 ,  H01L29/7881 ,  H01L29/792 ,  H01L45/1206 ,  H01L45/1253

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes fin-type stacked layer structures. Each of the structures includes semiconductor layers stacked in a perpendicular direction. Assist gate electrodes are disposed in an in-plane direction and divided on a surface in the perpendicular direction of the structures.

公开(公告)号：US20120218802A1

公开(公告)日：2012-08-30

申请号：US13403398

申请日：2012-02-23

申请人： Takao MARUKAME ,  Tomoaki INOKUCHI ,  Hideyuki SUGIYAMA ,  Mizue ISHIKAWA ,  Yoshiaki SAITO ,  Atsuhiro KINOSHITA ,  Kosuke TATSUMURA

发明人： Takao MARUKAME ,  Tomoaki INOKUCHI ,  Hideyuki SUGIYAMA ,  Mizue ISHIKAWA ,  Yoshiaki SAITO ,  Atsuhiro KINOSHITA ,  Kosuke TATSUMURA

IPC分类号： G11C15/02

CPC分类号： G11C15/02 ,  G11C11/161 ,  G11C15/046 ,  H01L27/228

摘要： One embodiment provides a content addressable memory, including: a pair of spin MOSFETs including: a first spin MOSFET whose magnetization state is set in accordance with stored data; and a second spin MOSFET whose magnetization state is set in accordance with the stored data, the second spin MOSFET being connected in parallel with the first spin MOSFET; a first wiring configured to apply a gate voltage so that any one of the first spin MOSFET and the second spin MOSFET becomes electrically conductive in accordance with search data; and a second wiring configured to apply a current to both of the first spin MOSFET and the second spin MOSFET.

摘要翻译： 一个实施例提供一种内容可寻址存储器，包括：一对自旋MOSFET，其包括：第一自旋MOSFET，其磁化状态根据存储的数据设置; 以及第二自旋MOSFET，其磁化状态根据存储的数据设定，第二自旋MOSFET与第一自旋MOSFET并联连接; 第一布线，被配置为施加栅极电压，使得第一自旋MOSFET和第二自旋MOSFET中的任何一个根据搜索数据变为导电; 以及配置为向第一自旋MOSFET和第二自旋MOSFET两者施加电流的第二布线。

公开(公告)号：US20120068241A1

公开(公告)日：2012-03-22

申请号：US13236734

申请日：2011-09-20

申请人： Kiwamu SAKUMA ,  Atsuhiro KINOSHITA

发明人： Kiwamu SAKUMA ,  Atsuhiro KINOSHITA

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L27/11578 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11565 ,  H01L29/785 ,  H01L29/792

摘要： According to one embodiment, a memory device includes first and second fin type stacked structures each includes first to i-th memory strings (i is a natural number except 1) that are stacked in a first direction, the first and second fin type stacked structures which extend in a second direction and which are adjacent in a third direction, a first portion connected to one end in the second direction of the first fin type stacked structure, a width in the third direction of the first portion being greater than a width in the third direction of the first fin type stacked structure, and a second portion connected to one end in the second direction of the second fin type stacked structure, a width in the third direction of the second portion being greater than a width in the third direction of the second fin type stacked structure.

摘要翻译： 根据一个实施例，存储器件包括第一和第二鳍式堆叠结构，每个第一和第二鳍式堆叠结构每个包括沿第一方向堆叠的第一至第i存储器串（i是除1之外的自然数），第一和第二鳍式堆叠结构 其在第二方向上延伸并且在第三方向上相邻，第一部分连接到第一鳍式堆叠结构的第二方向上的一端，第一部分的第三方向上的宽度大于第一方向上的宽度 第一鳍式堆叠结构的第三方向和与第二鳍式堆叠结构的第二方向的一端连接的第二部分，第二部分的第三方向上的宽度大于第三方向上的宽度 的第二鳍式堆叠结构。

公开(公告)号：US20070083342A1

公开(公告)日：2007-04-12

申请号：US11469706

申请日：2006-09-01

申请人： Hiroshi WATANABE ,  Atsuhiro KINOSHITA

发明人： Hiroshi WATANABE ,  Atsuhiro KINOSHITA

IPC分类号： G04F10/00

CPC分类号： G04F10/10

摘要： An electronic timer having a parallel unit, a current detecting unit, and a time measuring unit. The parallel unit is formed of a plurality of aging devices connected in parallel and configured to be turned on or off for a predetermined time after storing electric charges. Each aging device is a transistor which includes a floating gate. The current detecting unit detects a sum current flowing in the parallel unit when a voltage is applied between input and output terminals of the parallel unit. The time measuring unit measures a time required to resume the supplying of power after the interruption of power supplying, from the sum current detected by the current detecting unit.

摘要翻译： 具有并联单元，电流检测单元和时间测量单元的电子计时器。 并联单元由并联连接的多个老化装置形成，并且在存储电荷之后被配置为开启或关闭预定时间。 每个老化装置是包括浮动栅极的晶体管。 当在并行单元的输入和输出端之间施加电压时，电流检测单元检测在并联单元中流动的和电流。 所述时间测量单元根据由所述电流检测单元检测到的和电流来测量在供电中断之后恢复供电所需的时间。