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    Semiconductor integrated circuit device
    1.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US4550289A

    公开(公告)日：1985-10-29

    申请号：US453115

    申请日：1982-12-27

    申请人： Katsuhiko Kabashima ,  Yoshihiro Takemae ,  Shigeki Nozaki ,  Tsuyoshi Ohira ,  Hatsuo Miyahara ,  Masakazu Kanai ,  Seiji Enomoto

    发明人： Katsuhiko Kabashima ,  Yoshihiro Takemae ,  Shigeki Nozaki ,  Tsuyoshi Ohira ,  Hatsuo Miyahara ,  Masakazu Kanai ,  Seiji Enomoto

    IPC分类号： G01R31/26 ,  G06F11/00 ,  H01L21/66 ,  H01L21/822 ,  H01L27/00 ,  H01L27/04 ,  G01R31/28

    CPC分类号： G01R31/26 ,  G06F11/006

    摘要： A semiconductor integrated circuit (IC) device includes therein a test circuit. The test circuit operates to distinguish the power source level during the testing or ground level occurring at an internal node located inside the semiconductor chip. The test circuit includes a series-connected MIS transistor and an MIS diode. The gate of the MIS transistor is connected to the internal node. The MIS diode is connected to an external input/output (I/O) pin. The level at the internal node, i.e., the power source level or the ground level, can be distinguished by a first voltage level or a second voltage level applied to the external I/O pin, whichever enables a current to be drawn from the external I/O pin.

    摘要翻译： 半导体集成电路（IC）装置包括测试电路。 测试电路用于在测试期间区分电源电平或在位于半导体芯片内部的内部节点处发生地电平。 测试电路包括串联连接的MIS晶体管和MIS二极管。 MIS晶体管的栅极连接到内部节点。 MIS二极管连接到外部输入/输出（I / O）引脚。 可以通过施加到外部I / O引脚的第一电压电平或第二电压电平来区分内部节点的电平，即电源电平或接地电平，无论哪一个使外部电流从外部 I / O引脚。

    Buffer circuit
    3.
    发明授权
    Buffer circuit 失效
    缓冲电路

    公开(公告)号：US4458337A

    公开(公告)日：1984-07-03

    申请号：US354498

    申请日：1982-03-03

    申请人： Yoshihiro Takemae ,  Shigeki Nozaki ,  Tsutomu Mezawa ,  Katsuhiko Kabashima ,  Seiji Enomoto

    发明人： Yoshihiro Takemae ,  Shigeki Nozaki ,  Tsutomu Mezawa ,  Katsuhiko Kabashima ,  Seiji Enomoto

    IPC分类号： G11C11/413 ,  G11C11/408 ,  H03K3/356 ,  G11C13/00

    CPC分类号： H03K3/356017 ,  H03K3/35606

    摘要： A buffer circuit comprises a flip-flop which is receives an external input via a first input circuit and a reference voltage via a second input circuit. Internal complementary outputs are then produced via an output circuit. The flip-flop cooperates with at least one level setting device by way of a second input circuit. The level setting device functions to produce a voltage level to deactivate the second input circuit during activation of the flip-flop.

    摘要翻译： 缓冲电路包括经由第一输入电路接收外部输入的触发器和经由第二输入电路的参考电压。 然后通过输出电路产生内部互补输出。 触发器通过第二输入电路与至少一个电平设置装置协作。 电平设置装置用于产生电压电平，以在触发器激活期间停用第二输入电路。

    Address Buffer
    4.
    发明授权
    Address Buffer 失效
    地址缓冲区

    公开(公告)号：US4451908A

    公开(公告)日：1984-05-29

    申请号：US354499

    申请日：1982-03-03

    申请人： Yoshihiro Takemae ,  Shigeki Nozaki ,  Katsuhiko Kabashima ,  Seiji Enomoto ,  Tsutomu Mezawa

    发明人： Yoshihiro Takemae ,  Shigeki Nozaki ,  Katsuhiko Kabashima ,  Seiji Enomoto ,  Tsutomu Mezawa

    IPC分类号： G11C11/403 ,  G11C11/406 ,  G11C11/408 ,  G11C11/40

    CPC分类号： G11C11/4082 ,  G11C11/406

    摘要： An address buffer for a dynamic memory includes a flip-flop. The flip-flop is coupled at its one input/output terminal with both a first input circuit and a third input circuit connected in parallel with each other and at its other input/output terminal with a second input circuit. The second input circuit receives a reference voltage and is activated by an external address timing clock during a normal operation mode. The first input circuit is also activated by the external address timing clock, but receives an external address. The third input circuit receives an internal refresh address and is activated by an internal refresh address. The address buffer cooperates with a switcher which produces the internal refresh address timing clock and the external address timing clock, alternatively, by switching a basic timing clock generated by an address drive clock generator.

    摘要翻译： 用于动态存储器的地址缓冲器包括触发器。 触发器在其一个输入/输出端子处与第一输入电路和第三输入电路耦合，第一输入电路和第三输入电路彼此并联并且在其另一输入/输出端与第二输入电路连接。 第二输入电路接收参考电压，并在正常操作模式期间由外部地址定时时钟激活。 第一个输入电路也由外部地址定时时钟激活，但接收一个外部地址。 第三输入电路接收内部刷新地址，并由内部刷新地址激活。 地址缓冲器与产生内部刷新地址定时时钟和外部地址定时时钟的切换器配合，或者通过切换由地址驱动时钟发生器产生的基本定时时钟。

    Buffer circuit including a current leak circuit for maintaining the charged voltages
    5.
    发明授权
    Buffer circuit including a current leak circuit for maintaining the charged voltages 失效
    缓冲电路包括用于维持充电电压的电流泄漏电路

    公开(公告)号：US4447745A

    公开(公告)日：1984-05-08

    申请号：US322719

    申请日：1981-11-18

    申请人： Yoshihiro Takemae ,  Seiji Enomoto ,  Shigeki Nozaki ,  Tsutomu Mezawa ,  Katsuhiko Kabashima

    发明人： Yoshihiro Takemae ,  Seiji Enomoto ,  Shigeki Nozaki ,  Tsutomu Mezawa ,  Katsuhiko Kabashima

    IPC分类号： G11C11/417 ,  G06F1/04 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/418 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/096 ,  H03K5/135

    CPC分类号： G11C11/4076 ,  G11C11/418 ,  H03K19/01735 ,  H03K19/01855

    摘要： A semiconductor circuit used as a buffer circuit having an input stage circuit for receiving an input clock signal and an inverted input clock signal, a bootstrap circuit including a transistor for receiving the output of the input stage circuit and for maintaining the gate voltage of the transistor at a high level during the standby period, and an output circuit, including a transistor which is switched on and off by the output of the bootstrap circuit, for generating an output clock signal; the semiconductor circuit further comprising a current leak circuit for maintaining, during the standby period, the voltage of a point in the semiconductor circuit which is charged during the standby period at the value corresponding to the voltage of the power source, whereby the delay of the output clock signal, caused of the fluctuation by the voltage of the power supply during the standby period, is improved and then the high speed access time in the dynamic memory is carried out.

    摘要翻译： 一种用作缓冲电路的半导体电路，具有用于接收输入时钟信号和反相输入时钟信号的输入级电路，自举电路包括用于接收输入级电路的输出并保持晶体管的栅极电压的晶体管 在待机期间处于高电平;以及输出电路，包括由所述自举电路的输出接通和断开的晶体管，用于产生输出时钟信号; 所述半导体电路还包括电流泄漏电路，用于在所述待机期间保持所述半导体电路中在所述待机期间中以与所述电源的电压对应的值被充电的点的电压，由此所述延迟 在待机期间由电源的电压引起的输出时钟信号被提高，然后执行动态存储器中的高速访问时间。

    Semiconductor memory device
    8.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US4602356A

    公开(公告)日：1986-07-22

    申请号：US445921

    申请日：1982-12-01

    申请人： Shigeki Nozaki ,  Yoshihiro Takemae ,  Seiji Enomoto

    发明人： Shigeki Nozaki ,  Yoshihiro Takemae ,  Seiji Enomoto

    IPC分类号： G11C11/41 ,  G11C7/00 ,  G11C8/00 ,  G11C8/18 ,  G11C11/407 ,  G11C11/408 ,  G11C11/413

    CPC分类号： G11C8/18

    摘要： A semiconductor memory device operates under a so-called address multiplex access method. A row part of the device is enabled by receiving a row address strobe (RAS) signal. A column part of the device is enabled by simultaneously receiving both a column address strobe (CAS) signal and a timing control signal supplied from the row part during its enable state. A column address buffer in the column part is enabled by simultaneously receiving both the CAS signal and a timing control signal. The timing control signal is produced from a circuit when it detects and holds the RAS signal.

    摘要翻译： 半导体存储器件以所谓的地址复用存取方式工作。 器件的一部分通过接收行地址选通（＆upbar＆R）信号来使能。 器件的列部分通过在其使能状态期间同时接收列地址选通（＆upbar＆C）信号和从行部分提供的定时控制信号来启用。 列部分中的列地址缓冲器通过同时接收＆upbar＆C信号和定时控制信号而被使能。 定时控制信号从电路产生，当它检测并保持＆amp; R＆R信号。

    Semiconductor memory device having flip-flop circuits
    10.
    发明授权
    Semiconductor memory device having flip-flop circuits 失效
    具有触发电路的半导体存储器件

    公开(公告)号：US4291394A

    公开(公告)日：1981-09-22

    申请号：US87389

    申请日：1979-10-22

    申请人： Masao Nakano ,  Tomio Nakano ,  Yoshihiro Takemae ,  Katsuhiko Kabashima

    发明人： Masao Nakano ,  Tomio Nakano ,  Yoshihiro Takemae ,  Katsuhiko Kabashima

    IPC分类号： G11C11/419 ,  G11C5/06 ,  G11C11/409 ,  G11C11/4096 ,  G11C11/4099 ,  H03K3/356 ,  G11C11/40

    CPC分类号： G11C5/063 ,  G11C11/4096 ,  G11C11/4099

    摘要： A semiconductor memory device having flip-flop circuits, in which first and second bit lines are connected to each of the flip-flop circuits as a sense amplifier, the potential of the second bit line being opposite to the potential of the first bit line, and the first and second data bus lines cross perpendicularly to the first and second bit lines, respectively, the first and second dummy lines are arranged in parallel with the first and second data bus lines respectively, in order to prevent erroneous operation of an I/O amplifier connected to the first and second data bus lines.

    摘要翻译： 一种具有触发电路的半导体存储器件，其中第一和第二位线连接到作为读出放大器的每个触发器电路，第二位线的电位与第一位线的电位相反， 并且第一和第二数据总线分别与第一和第二位线垂直交叉，第一和第二虚拟线分别与第一和第二数据总线线并排布置，以防止I / O放大器连接到第一和第二数据总线。