公开(公告)号：US06839806B2

公开(公告)日：2005-01-04

申请号：US09941696

申请日：2001-08-30

申请人： Yoshiki Murakami ,  Masaru Koyanagi ,  Hideya Akashi

发明人： Yoshiki Murakami ,  Masaru Koyanagi ,  Hideya Akashi

IPC分类号： G06F12/08 ,  G06F12/12 ,  G06F12/00

CPC分类号： G06F12/0855 ,  G06F12/0831

摘要： A cache system comprising a cache tag buffer 270 for storing a part of a cache tag memory 260. When a memory processing request is issued from a processor 10, a cache control means 280 retrieves both of the cache tag memory 260 and the cache tag buffer 270. If a target cache block is present in the cache tag buffer 270, then, without waiting for a retrieval result of the cache tag memory 260, the cache control circuit 280 accesses the cache data memory 250 using information of the cache block.

公开(公告)号：US06606688B1

公开(公告)日：2003-08-12

申请号：US09642002

申请日：2000-08-21

申请人： Masaru Koyanagi ,  Disuke Yamane ,  Hideya Akashi ,  Yuji Tsushima ,  Tadayuki Sakakibara

发明人： Masaru Koyanagi ,  Disuke Yamane ,  Hideya Akashi ,  Yuji Tsushima ,  Tadayuki Sakakibara

IPC分类号： G06F1200

CPC分类号： G06F12/0862

摘要： A cache controller stores pre-set variables for pre-fetch block size and stride value. A cache controller receives an access request for the main memory from the processor, and generates a pre-fetch request based an the access request and the variables. The cache controller reads data from main memory based on the generated pre-fetch request and writes this data to the cache memory.

摘要翻译： 缓存控制器存储用于预取块大小和步幅值的预设变量。 缓存控制器从处理器接收对主存储器的访问请求，并且基于访问请求和变量生成预取请求。 高速缓存控制器基于生成的预取请求从主存储器读取数据，并将该数据写入缓存存储器。

公开(公告)号：US08736346B2

公开(公告)日：2014-05-27

申请号：US13524391

申请日：2012-06-15

申请人： Yuui Shimizu ,  Masaru Koyanagi

发明人： Yuui Shimizu ,  Masaru Koyanagi

IPC分类号： H03L5/00

摘要： According to one embodiment, a level shift circuit includes a plurality of level shift units which are connected to each other and in which the delay time of the rising edge of an output voltage is different from the delay time of the falling edge of the output voltage. The delay time of the rising edge of the output voltage from the previous level shift unit is compensated by the delay time of the falling edge of the output voltage from the next level shift unit, and the delay time of the falling edge of the output voltage from the previous level shift unit is compensated by the delay time of the rising edge of the output voltage from the next level shift unit.

摘要翻译： 根据一个实施例，电平移位电路包括彼此连接的多个电平移位单元，其中输出电压的上升沿的延迟时间与输出电压的下降沿的延迟时间不同 。 来自先前电平移位单元的输出电压的上升沿的延迟时间由下一个电平移位单元的输出电压的下降沿的延迟时间补偿，并且输出电压的下降沿的延迟时间 来自先前电平移位单元的输出电压的上升沿的延迟时间由下一个电平移位单元补偿。

公开(公告)号：US08405432B2

公开(公告)日：2013-03-26

申请号：US12963114

申请日：2010-12-08

申请人： Masaru Koyanagi ,  Yasufumi Kajiyama ,  Ryo Fukuda ,  Fumiyoshi Matsuoka ,  Yasuhiro Suematsu

发明人： Masaru Koyanagi ,  Yasufumi Kajiyama ,  Ryo Fukuda ,  Fumiyoshi Matsuoka ,  Yasuhiro Suematsu

IPC分类号： H03K3/01

CPC分类号： H03K19/00384 ,  H03K19/01721

摘要： An output buffer circuit in accordance with an embodiment comprises a plurality of buffer circuits, each of the buffer circuits including a transistor operative to change an output signal of an output terminal in response to a change in an input signal, the output buffer circuit being configured to enable the plurality of buffer circuits to be driven selectively. Each of the plurality of buffer circuits includes a plurality of output transistors having respective current paths formed in parallel to one another between a fixed voltage terminal supplying a certain fixed voltage and an output terminal, and being selectively rendered in an operable state in accordance with a control signal provided from external. The plurality of output transistors included in each of the plurality of buffer circuits are formed having a certain size ratio.

摘要翻译： 根据实施例的输出缓冲器电路包括多个缓冲电路，每个缓冲电路包括一个晶体管，用于响应于输入信号的变化而改变输出端的输出信号，该输出缓冲电路被配置 以使得能够选择性地驱动多个缓冲电路。 多个缓冲电路中的每一个包括多个输出晶体管，其具有在提供一定固定电压的固定电压端子和输出端子之间彼此并联形成的各自的电流路径，并且根据 控制信号由外部提供。 包含在多个缓冲电路的每一个中的多个输出晶体管形成为具有一定的尺寸比。

公开(公告)号：US20110128063A1

公开(公告)日：2011-06-02

申请号：US12884533

申请日：2010-09-17

申请人： Ryo Fukuda ,  Masaru Koyanagi

发明人： Ryo Fukuda ,  Masaru Koyanagi

IPC分类号： H03L5/00

CPC分类号： H03K3/356113

摘要： According to one embodiment, a semiconductor integrated circuit includes first and second level shift circuits. The first level shifter includes a plurality of transistors and is connected to a power source voltage supply node of a first power source system and to which a first signal of a second power source system and a level inversion signal of the first signal are input. The second level shifter includes a plurality of transistors and is connected to the power source voltage supply node of the first power source system and to which the level inversion signal of the first signal of the second power source system and an output signal of the first level shifter are input. The first and second level shifters have substantially the same circuit configuration and driving abilities of corresponding ones of the transistors in the first and second level shifters are substantially set equal.

摘要翻译： 根据一个实施例，半导体集成电路包括第一和第二电平移位电路。 第一电平移位器包括多个晶体管，并连接到第一电源系统的电源电压供应节点，第二电源系统的第一信号和第一信号的电平反转信号被输入到该第一电源系统。 第二电平移位器包括多个晶体管，并连接到第一电源系统的电源电压供应节点，并且第二电源系统的第一信号的电平反转信号和第一电平系统的输出信号 移位器被输入。 第一和第二电平移位器具有基本上相同的电路配置，并且第一和第二电平移位器中对应的晶体管的驱动能力基本上相等。

公开(公告)号：US20090051020A1

公开(公告)日：2009-02-26

申请号：US12035813

申请日：2008-02-22

申请人： Takashi Taira ,  Masaru Koyanagi

发明人： Takashi Taira ,  Masaru Koyanagi

IPC分类号： H01L21/58 ,  H01L23/495

CPC分类号： H01L23/4951 ,  H01L23/49537 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/49 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/30107 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A semiconductor memory device includes: A method of manufacturing a semiconductor device, wherein a semiconductor chip is mounted on a lead frame including a plurality of lead lines, and terminals included in the semiconductor chip are connected to the lead lines, thereby to manufacture the semiconductor device, comprising the steps of: arranging distal end parts of the plurality of lead lines at equal intervals along a direction of a first axis, the distal end parts being connected with the terminals included in the semiconductor chip; arranging terminal parts for inputting/outputting signals, at equal intervals along a direction of a second axis; shaping intermediate parts for connecting the distal end parts and the terminal parts, so as to be bent between the distal end parts and the terminal parts; forming a half number of the plurality of lead lines and the remaining half number of the plurality of lead lines so as to have a shape of line symmetry with respect to the second axis; and mounting the semiconductor chip on a front surface side of a package.

摘要翻译： 半导体存储器件包括：半导体器件的制造方法，其中将半导体芯片安装在包括多根引线的引线框架上，并且包含在半导体芯片中的端子连接到引线，从而制造半导体 装置，包括以下步骤：沿着第一轴线的方向以相等的间隔布置多条引线的远端部分，所述远端部分与包括在所述半导体芯片中的端子连接; 沿着第二轴的方向以等间隔布置用于输入/输出信号的端子部分; 成形用于连接远端部分和端子部分的中间部分，以在远端部分和端部部分之间弯曲; 形成所述多根引线的半数和所述多根引线的剩余的半数，使其相对于所述第二轴具有线对称的形状; 以及将半导体芯片安装在封装的前表面侧。

公开(公告)号：US06801144B2

公开(公告)日：2004-10-05

申请号：US10678742

申请日：2003-10-02

申请人： Katsuki Matsudera ,  Masaru Koyanagi ,  Kazuhide Yoneya ,  Toshiki Hisada

发明人： Katsuki Matsudera ,  Masaru Koyanagi ,  Kazuhide Yoneya ,  Toshiki Hisada

IPC分类号： H03M900

CPC分类号： G11C7/1036

摘要： An input/output circuit inputs/outputs serial data. A register section comprises a first and a second register. The first register converts the serial data into parallel data. The second register converts parallel data into serial data. A first control signals supply a conversion timing for each bit when the serial data are converted into the parallel data. A second control signals supply a conversion timing for each bit when the parallel data are converted into the serial data. The signal generating circuit controls a timing of rise or fall of the first control signals and sets which of the memory cells should store a value for each bit, of the serial data, and controls a timing of rise or fall of the second control signals and sets which number of value of the serial data should be the value for each bit, of the parallel data read from the memory cells.

摘要翻译： 输入/输出电路输入/输出串行数据。 寄存器部分包括第一和第二寄存器。 第一个寄存器将串行数据转换为并行数据。 第二个寄存器将并行数据转换为串行数据。 当串行数据被转换成并行数据时，第一控制信号为每个位提供转换定时。 当并行数据被转换成串行数据时，第二控制信号为每个位提供转换定时。 信号发生电路控制第一控制信号的上升或下降的定时，并设置哪个存储单元应存储串行数据的每个位的值，并且控制第二控制信号的上升或下降的定时，以及 将串行数据的值的数量设置为从存储器单元读取的并行数据的每个位的值。

公开(公告)号：US06577551B2

公开(公告)日：2003-06-10

申请号：US10007148

申请日：2001-12-04

申请人： Mikihiko Ito ,  Masaru Koyanagi ,  Takahiko Hara ,  Satoru Takase ,  Tohru Kimura

发明人： Mikihiko Ito ,  Masaru Koyanagi ,  Takahiko Hara ,  Satoru Takase ,  Tohru Kimura

IPC分类号： G11C700

CPC分类号： G11C17/18 ,  G11C17/16

摘要： A semiconductor integrated circuit includes a control data storage circuit (6) having nonvolatile storage devices with programmed control data and a latch circuit for holding data read out from the storage devices, and a read control circuit (7) for controlling read operations of the control data, which are built in a semiconductor chip. The control data storage circuit (6) is divided into groups (1, 2), and the read control circuit (7) generates read control signals for the groups (1, 2) at different timings, using an output of an internal potential detecting circuit 41 as the timing reference, thereby preventing the peak of power consumption from unacceptably rising during reading operations.

摘要翻译： 半导体集成电路包括具有编程控制数据的非易失性存储装置的控制数据存储电路（6）和用于保存从存储装置读出的数据的锁存电路，以及用于控制控制的读取操作的读取控制电路（7） 数据，内置在半导体芯片中。 控制数据存储电路（6）被分成组（1,2），读取控制电路（7）使用内部电位检测的输出在不同的定时产生用于组（1,2）的读取控制信号 电路41作为定时参考，从而防止功耗峰值在读取操作期间不可接受地上升。

公开(公告)号：US06498741B2

公开(公告)日：2002-12-24

申请号：US09746890

申请日：2000-12-21

申请人： Katsuki Matsudera ,  Kazuhide Yoneya ,  Toshiki Hisada ,  Masaru Koyanagi ,  Natsuki Kushiyama ,  Kaoru Nakagawa ,  Takahiko Hara

发明人： Katsuki Matsudera ,  Kazuhide Yoneya ,  Toshiki Hisada ,  Masaru Koyanagi ,  Natsuki Kushiyama ,  Kaoru Nakagawa ,  Takahiko Hara

IPC分类号： G11C506

CPC分类号： G11C5/063

摘要： A semiconductor memory device is provided which ensures the symmetry of memory data transmission time and a high-speed operation and has large write/read operation margin with no need of increasing the chip area. By placing a horizontally long peripheral circuit section in the middle in the vertical direction of a semiconductor chip, placing a vertically long shift register section above and below and perpendicularly to the peripheral circuit section, and making the memory core and shift register arrangement symmetrical in the horizontal direction, the data/signal lines between the memory core and the shift register section can be made short and the symmetry of the interconnections can be maintained, which allows the implementation of a high-speed and large-margin semiconductor memory device. In addition, a faster semiconductor memory can be obtained by forming the shift register section by stacking shift registers each corresponding to a data block and selecting the order in which the shift registers are stacked so that the length of interconnections between the peripheral circuit and the shift register is minimized.

摘要翻译： 提供一种半导体存储器件，其确保存储器数据传输时间和高速操作的对称性，并且具有大的写入/读取操作裕度，而不需要增加芯片面积。 通过在半导体芯片的垂直方向上的中间放置一个水平长的外围电路部分，将垂直长的移位寄存器部分设置在周边电路部分的上下方向并垂直于外围电路部分，并使存储器核心和移位寄存器装置在 水平方向，可以使存储器芯和移位寄存器部分之间的数据/信号线短，并且可以保持互连的对称性，这允许实现高速和大面积的半导体存储器件。 另外，通过将每个对应于数据块的移位寄存器堆叠并选择堆叠移位寄存器的顺序，使得外围电路与移位之间的互连长度可以获得更快的半导体存储器 寄存器被最小化。

公开(公告)号：US06496442B2

公开(公告)日：2002-12-17

申请号：US10076558

申请日：2002-02-19

申请人： Masaru Koyanagi ,  Kaoru Nakagawa ,  Takahiko Hara ,  Satoru Takase

发明人： Masaru Koyanagi ,  Kaoru Nakagawa ,  Takahiko Hara ,  Satoru Takase

IPC分类号： G11C800

CPC分类号： G11C8/18 ,  G11C8/12 ,  G11C11/406

摘要： A DRAM, including a plurality of banks each having a plurality of sub-arrays, and sense amplifier circuits commonly shared by sub-arrays in different banks, has a row access mode for activating a sub-array selected from each bank for reading or writing data, and a refresh mode for activating a plurality of sub-arrays in each bank and refreshing memory cell data therein at substantially the same timing. Sub-arrays in each bank activated at substantially the same timing in the refresh mode are more than sub-arrays in each bank activated in the row access model. Thereby, occurrence of operation constrains is minimized to ensure high-speed operation and improve the system performance of DRAMs employing the non-independent bank system.

摘要翻译： 包括多个具有多个子阵列的多个存储体的DRAM和通常由不同存储体中的子阵列共享的读出放大器电路具有用于激活从每个存储体中选择的用于读取或写入的子阵列的行访问模式 数据和刷新模式，用于激活每个存储体中的多个子阵列，并以基本相同的定时刷新存储器单元数据。 在刷新模式中基本上相同的定时激活的每个存储体中的子阵列多于在行存取模型中激活的每个存储体中的子阵列。 由此，操作约束的发生被最小化以确保高速操作，并且提高采用非独立银行系统的DRAM的系统性能。