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    Semiconductor integrated circuit having circuit for transmitting input signal
    1.
    发明授权
    Semiconductor integrated circuit having circuit for transmitting input signal 有权

    公开(公告)号：US06518790B2

    公开(公告)日：2003-02-11

    申请号：US09940622

    申请日：2001-08-29

    申请人： Yoshiki Wada ,  Harufusa Kondoh

    发明人： Yoshiki Wada ,  Harufusa Kondoh

    IPC分类号： H03K190175

    CPC分类号： H01L27/088 ,  H03K5/151

    摘要： A semiconductor integrated circuit includes inverters and a PMOS transistor which are disposed for a first signal, and inverters and a PMOS transistor which are disposed for a second signal substantially complementary to the first signal. By the transistors, potentials of signal lines are driven. A transistor for 1.8 V is used for each of the transistors and the inverters at the rear stage. A transistor for 3.3 V is used for each of the inverters at the front stage. With the configuration, the complementary signals are transmitted at optimum timings.

    High impedance detecting circuit and interface circuit
    2.
    发明授权
    High impedance detecting circuit and interface circuit 失效
    高阻抗检测电路和接口电路

    公开(公告)号：US5874835A

    公开(公告)日：1999-02-23

    申请号：US719888

    申请日：1996-09-25

    申请人： Masahiko Ishiwaki ,  Harufusa Kondoh ,  Hiromi Notani

    发明人： Masahiko Ishiwaki ,  Harufusa Kondoh ,  Hiromi Notani

    IPC分类号： G01R31/317 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/00 ,  H03K19/02

    CPC分类号： H03K19/003

    摘要： A voltage applying means applies a voltage which determines the logical value of a node to the node, with the signal at the node fixed. Then, an applied voltage removing means removes the voltage applied by the voltage applying means. First and second detecting means detects the logical value of the node before and after the voltage application and removal of the applied voltage. A judging means compares the results of detection of the first and second detecting means to judge whether or not the node is at a high impedance.

    摘要翻译： 电压施加装置将确定节点的逻辑值的电压施加到节点，同时节点处的信号被固定。 然后，施加的电压去除装置去除由电压施加装置施加的电压。 第一和第二检测装置检测在施加电压和施加的电压的去除之前和之后节点的逻辑值。 判断装置比较第一和第二检测装置的检测结果，以判断节点是否处于高阻抗。

    Output circuit and interface system comprising the same
    3.
    发明授权
    Output circuit and interface system comprising the same 失效
    输出电路和包含它的接口系统

    公开(公告)号：US5235222A

    公开(公告)日：1993-08-10

    申请号：US813627

    申请日：1991-12-26

    申请人： Harufusa Kondoh ,  Hiromi Notani

    发明人： Harufusa Kondoh ,  Hiromi Notani

    IPC分类号： H04L25/02 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/0185 ,  H04Q3/42

    CPC分类号： H03K19/00361 ,  H03K19/018557

    摘要： An output circuit 1 comprises a constant current source 11, a switch 12, and an output pad 14. The switch 12 is connected between the constant current source 11 and the output pad 14. A transmission path 3 is connected to the output pad 14. The transmission path 3 is coupled to a terminator voltage V.sub.TT by a resistor for pull up. Reflection of a signal or generation of noise can be suppressed by bringing the resistance value of the resistor 4 close to a characteristic impedance of the transmission path 3. A voltage amplitude on the transmission path 3 can be determined arbitrarily by adjusting current value of the constant current source 11 and resistance value of the resistor 4.

    摘要翻译： 输出电路1包括恒流源11，开关12和输出垫14.开关12连接在恒流源11和输出垫14之间。传输路径3连接到输出焊盘14。 传输路径3通过用于上拉的电阻器耦合到终端电压VTT。 可以通过使电阻器4的电阻值接近传输路径3的特性阻抗来抑制信号的反射或产生噪声。传输路径3上的电压振幅可以通过调整常数的电流值来任意确定 电流源11和电阻器4的电阻值。

    Input circuit operable under different source voltages in semiconductor integrated circuit
    4.
    发明授权
    Input circuit operable under different source voltages in semiconductor integrated circuit 失效
    输入电路可在半导体集成电路中的不同电源电压下工作

    公开(公告)号：US4965469A

    公开(公告)日：1990-10-23

    申请号：US461967

    申请日：1990-01-08

    申请人： Harufusa Kondoh ,  Takeo Nakabayashi

    发明人： Harufusa Kondoh ,  Takeo Nakabayashi

    IPC分类号： H03K5/08 ,  G05F1/46 ,  G11C11/409 ,  H03K5/02 ,  H03K19/00 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/08

    CPC分类号： H03K19/018521 ,  G05F1/462 ,  H03K19/017518

    摘要： An input circuit provided in a MOS semiconductor IC having a compatible characteristics with an external TTL circuit. The input circuit comprises a circuit for generating a fixed reference voltage without depending on any supplied source voltage level, and a circuit for comparing the input voltage with the reference voltage. Therefore, a fixed margin for detecting the logic value of the input signal can be ensured regardless of whether the source voltage supplied is either 3.0 volts or 5.0 volts.

    摘要翻译： 提供在与外部TTL电路具有兼容特性的MOS半导体IC中的输入电路。 输入电路包括用于不依赖于所提供的源电压电平产生固定参考电压的电路和用于将输入电压与参考电压进行比较的电路。 因此，可以确保用于检测输入信号的逻辑值的固定裕度，而不管所提供的源电压是3.0伏还是5.0伏。

    Digital synchronous circuit for stably generating output clock synchronized with input data
    5.
    发明授权
    Digital synchronous circuit for stably generating output clock synchronized with input data 失效
    数字同步电路，用于稳定地产生与输入数据同步的输出时钟

    公开(公告)号：US06987825B1

    公开(公告)日：2006-01-17

    申请号：US09584728

    申请日：2000-06-01

    申请人： Tsutomu Yoshimura ,  Harufusa Kondoh

    发明人： Tsutomu Yoshimura ,  Harufusa Kondoh

    IPC分类号： H04L7/00

    CPC分类号： H03K5/135 ,  H03K2005/00156 ,  H04L7/0338

    摘要： The present digital synchronous circuit includes a clock generating circuit for outputting a plurality of clock signals CLK1 to CLKn, a plurality of first latch circuits, each for receiving an input data signal DIN at a data input terminal and for receiving a corresponding clock signal at a clock input terminal, a plurality of second latch circuits, each for latching, in response to the receipt of a control signal LC, an output signal from a corresponding first latch circuit, and a control circuit for receiving input data signal DIN to generate control signal LC. Control circuit outputs control signal LC after a delay of a prescribed period of time after the change in input data signal DIN. As a result, the adverse influence of the meta-stable state that occurs when sampling an asynchronous input data signal DIN is avoided, while at the same time, the chip size and power consumption are limited.

    摘要翻译： 本数字同步电路包括用于输出多个时钟信号CLK 1至CLK n的时钟产生电路，多个第一锁存电路，每个用于在数据输入端接收输入数据信号DIN，并用于接收相应的时钟信号 时钟输入端子，多个第二锁存电路，每个用于响应于控制信号LC的接收而锁存来自对应的第一锁存电路的输出信号，以及用于接收输入数据信号DIN以产生控制的控制电路 信号LC。 控制电路在输入数据信号DIN改变后的规定时间内延迟输出控制信号LC。 结果，避免了在对异步输入数据信号DIN采样时发生的元稳定状态的不利影响，同时芯片尺寸和功耗受到限制。

    Semiconductor integrated circuit
    6.
    发明授权
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号：US06504404B2

    公开(公告)日：2003-01-07

    申请号：US10033924

    申请日：2002-01-03

    申请人： Hideki Uchiki ,  Harufusa Kondoh

    发明人： Hideki Uchiki ,  Harufusa Kondoh

    IPC分类号： H03K512

    CPC分类号： H03F3/45708 ,  H03F2203/45401

    摘要： A semiconductor integrated circuit includes a differential amplifier, a common level detection circuit which detects a common level of input signals A and B, and a bias generation circuit which generates a bias voltage to be applied to a gate terminal of a MOS transistor that is a constant-current power source of the differential amplifier based on the detected level.

    摘要翻译： 半导体集成电路包括差分放大器，检测公共电平的输入信号A和B的公共电平检测电路，以及偏置产生电路，该偏置产生电路产生施加到MOS晶体管的栅极端子的偏置电压， 基于检测电平的差分放大器的恒流电源。

    Digital data transmission system
    7.
    发明授权
    Digital data transmission system 失效
    数字数据传输系统

    公开(公告)号：US06396888B1

    公开(公告)日：2002-05-28

    申请号：US09032944

    申请日：1998-03-02

    申请人： Hiromi Notani ,  Harufusa Kondoh ,  Masahiko Ishiwaki ,  Tsutomu Yoshimura

    发明人： Hiromi Notani ,  Harufusa Kondoh ,  Masahiko Ishiwaki ,  Tsutomu Yoshimura

    IPC分类号： H04L706

    CPC分类号： H03L7/0805 ,  H03L7/0812 ,  H03L7/0891 ,  H04J3/0614 ,  H04L7/0008 ,  H04L7/02 ,  H04L7/04

    摘要： A digital data transmission system for transmitting digital data, a frame pulse signal, and a clock using a required minimum number of signal lines and with a simple circuit structure is provided. A signal separation circuit (46) that receives a multiple clock (CKFP) which is a frame pulse signal (FP) multiplexed with a clock (CK) includes a clock recovery circuit (47) for reproducing a recovered clock (RCK) by synchronization with the multiple clock (CKFP) using a synchronization loop, and a frame pulse signal separation circuit (48) for separating a recovered frame pulse signal (RFP) from the multiple clock (CKFP) on the basis of the recovered clock (RCK).

    摘要翻译： 提供了一种用于使用所需的最小数量的信号线和简单的电路结构来发送数字数据，帧脉冲信号和时钟的数字数据传输系统。 接收与时钟（CK）复用的帧脉冲信号（FP）的多时钟（CKFP）的信号分离电路（46）包括：时钟恢复电路（47），用于通过与时钟（CK）同步再现再生时钟（RCK） 使用同步环路的多个时钟（CKFP）和基于恢复时钟（RCK）从多个时钟（CKFP）分离恢复的帧脉冲信号（RFP）的帧脉冲信号分离电路（48）。

    Bus system and bus sense amplifier with precharge means
    8.
    发明授权
    Bus system and bus sense amplifier with precharge means 失效
    总线系统和总线读出放大器具有预充电功能

    公开(公告)号：US5661417A

    公开(公告)日：1997-08-26

    申请号：US521724

    申请日：1995-08-31

    申请人： Harufusa Kondoh

    发明人： Harufusa Kondoh

    IPC分类号： G06F3/00 ,  H03K19/00 ,  H03K19/0185 ,  H03K19/094 ,  H04L25/02

    CPC分类号： H04L25/0294 ,  H03K19/0016 ,  H03K19/01855 ,  H04L25/0272

    摘要： A purpose of this invention is to realize a bus system of high speed and low power consumption type applying precharge. A precharge signal input line (4), a power source potential (V.sub.DD), and a bus (1) are connected to a gate electrode, a drain region, and a source region of a first MOS transistor (MNP), the power source potential (V.sub.DD), a node (N1), and the bus (1) are connected to a gate electrode, a drain region, and a source region of a second MOS transistor (MN1), and the precharge signal input line (4) through an inverter (3), the power source potential (V.sub.DD), and the node (N1) are connected to a gate electrode, a source region, and a drain region of a third MOS transistor (MP1), respectively. In precharge period (PC=H), the potential of the bus (BUS) rises gradually, and the both transistors (MNP, MN1) are turned off. In EVL period (PC=L), when data is output from a register (6), the potential of the bus (BUS) drops, and the second MOS transistor (MN1) is turned on.

    摘要翻译： 本发明的目的是实现一种应用预充电的高速和低功耗型总线系统。 预充电信号输入线（4），电源电位（VDD）和总线（1）连接到第一MOS晶体管（MNP）的栅极，漏极区域和源极区域，电源 电位（VDD），节点（N1）和总线（1）连接到第二MOS晶体管（MN1）的栅电极，漏区和源极区，预充电信号输入线（4） 通过反相器（3），电源电位（VDD）和节点（N1）分别连接到第三MOS晶体管（MP1）的栅极电极，源极区域和漏极区域。 在预充电期间（PC = H），总线（BUS）的电位逐渐上升，两个晶体管（MNP，MN1）都断开。 在EVL周期（PC = L）中，当从寄存器（6）输出数据时，总线（BUS）的电位下降，第二MOS晶体管（MN1）导通。

    Priority processing of ATM cells using shift register stages
    10.
    发明授权
    Priority processing of ATM cells using shift register stages 失效
    使用移位寄存器阶段对ATM信元进行优先处理

    公开(公告)号：US5535202A

    公开(公告)日：1996-07-09

    申请号：US401138

    申请日：1995-03-08

    申请人： Harufusa Kondoh

    发明人： Harufusa Kondoh

    IPC分类号： G11C19/00 ,  H04L12/865 ,  H04L12/931 ,  H04Q3/00 ,  H04Q11/04 ,  H04L12/56

    CPC分类号： H04Q11/0478 ,  H04L2012/5651 ,  H04L2012/5652 ,  H04L2012/5681

    摘要： In order to obtain a buffer control shift register for an ATM switching unit for transmitting ATM cells which are stored in the unit while controlling the same in response to deadlines thereof, the unit comprises a comparator (53) for comparing dispatch times DPT.sub.0 of inputted ATM cells with those stored in a register (51). Registers (50, 51) are formed to be capable of bidirectional shifting (positive and negative directions along .gamma.). A shift/write control (54) rearwardly shifts data having a larger dispatch time in response to the result of comparison of the comparator (53), to write data of the inputted ATM cells in the vacated portion. It is possible to sequence data of the shift register from the frontmost stage in order of the dispatch times.

    摘要翻译： 为了获得一个ATM切换单元的缓冲器控制移位寄存器，用于发送存储在该单元中的ATM信元，同时响应于其最后期限而对其进行控制，该单元包括比较器（53），用于将输入的ATM的调度时间DPT0进行比较 存储在寄存器（51）中的单元。 寄存器（50,51）形成为能够进行双向移位（沿伽马的正向和负向）。 响应于比较器（53）的比较结果，移位/写入控制（54）向后移位具有较大调度时间的数据，以便在空出部分中写入输入的ATM信元的数据。 可以按照调度次序从最前面的阶段对移位寄存器的数据进行排序。