公开(公告)号：US20050014354A1

公开(公告)日：2005-01-20

申请号：US10916500

申请日：2004-08-12

申请人： Yoshio Ozawa ,  Masayuki Tanaka ,  Kiyotaka Miyano ,  Shigehiko Saida

发明人： Yoshio Ozawa ,  Masayuki Tanaka ,  Kiyotaka Miyano ,  Shigehiko Saida

IPC分类号： H01L29/78 ,  H01L29/49 ,  H01L21/338 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/4983 ,  H01L29/41783 ,  H01L29/6656

摘要： A semiconductor device includes a semiconductor device comprising a semiconductor substrate, source/drain regions formed in the semiconductor substrate, a gate insulation film formed on the semiconductor substrate, a gate electrode formed on the gate insulation film between the source/drain regions, and a gate sidewall spacer formed on side surfaces of the gate electrode, wherein the gate sidewall spacer is composed of silicon oxide containing 0.1-30 atomic % of chlorine.

摘要翻译： 半导体器件包括半导体器件，其包括半导体衬底，形成在半导体衬底中的源极/漏极区域，形成在半导体衬底上的栅极绝缘膜，形成在源极/漏极区域之间的栅极绝缘膜上的栅电极和 形成在栅电极的侧表面上的栅极侧壁间隔物，其中栅极侧壁间隔物由含有0.1-30原子％氯的氧化硅组成。

公开(公告)号：US07148158B2

公开(公告)日：2006-12-12

申请号：US10916500

申请日：2004-08-12

申请人： Yoshio Ozawa ,  Masayuki Tanaka ,  Kiyotaka Miyano ,  Shigehiko Saida

发明人： Yoshio Ozawa ,  Masayuki Tanaka ,  Kiyotaka Miyano ,  Shigehiko Saida

IPC分类号： H01L21/338 ,  H01L21/8238 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/44

CPC分类号： H01L29/4983 ,  H01L29/41783 ,  H01L29/6656

摘要： A semiconductor device includes a semiconductor device comprising a semiconductor substrate, source/drain regions formed in the semiconductor substrate, a gate insulation film formed on the semiconductor substrate, a gate electrode formed on the gate insulation film between the source/drain regions, and a gate sidewall spacer formed on side surfaces of the gate electrode, wherein the gate sidewall spacer is composed of silicon oxide containing 0.1–30 atomic % of chlorine.

公开(公告)号：US06774462B2

公开(公告)日：2004-08-10

申请号：US10278882

申请日：2002-10-24

申请人： Masayuki Tanaka ,  Yoshio Ozawa ,  Shigehiko Saida ,  Akira Goda ,  Mitsuhiro Noguchi ,  Yuichiro Mitani ,  Yoshitaka Tsunashima

发明人： Masayuki Tanaka ,  Yoshio Ozawa ,  Shigehiko Saida ,  Akira Goda ,  Mitsuhiro Noguchi ,  Yuichiro Mitani ,  Yoshitaka Tsunashima

IPC分类号： H01L2358

CPC分类号： H01L21/022 ,  H01L21/0217 ,  H01L21/28176 ,  H01L21/28202 ,  H01L21/28247 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/3185 ,  H01L21/76838 ,  H01L21/76897 ,  H01L29/513 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/792

摘要： Disclosed is a semiconductor device comprising a semiconductor substrate, a gate electrode, a first insulating film formed between the semiconductor substrate and the gate electrode, and a second insulating film formed along a top surface or a side surface of the gate electrode and including a lower silicon nitride film containing nitrogen, silicon and hydrogen and an upper silicon nitride film formed on the lower silicon nitride film and containing nitrogen, silicon and hydrogen, and wherein a composition ratio N/Si of nitrogen (N) to silicon (Si) in the lower silicon nitride film is higher than that in the upper silicon nitride film.

摘要翻译： 公开了一种半导体器件，包括半导体衬底，栅电极，形成在半导体衬底和栅电极之间的第一绝缘膜，以及沿着栅电极的顶表面或侧表面形成的第二绝缘膜， 包含氮，硅和氢的氮化硅膜和形成在下部氮化硅膜上并含有氮，硅和氢的上部氮化硅膜，并且其中氮（N）与硅（Si）的组成比N / Si在 下氮化硅膜比上述氮化硅膜高。

公开(公告)号：US07372113B2

公开(公告)日：2008-05-13

申请号：US10880508

申请日：2004-07-01

申请人： Masayuki Tanaka ,  Yoshio Ozawa ,  Shigehiko Saida ,  Akira Goda ,  Mitsuhiro Noguchi ,  Yuichiro Mitani ,  Yoshitaka Tsunashima

发明人： Masayuki Tanaka ,  Yoshio Ozawa ,  Shigehiko Saida ,  Akira Goda ,  Mitsuhiro Noguchi ,  Yuichiro Mitani ,  Yoshitaka Tsunashima

IPC分类号： H01L21/314

CPC分类号： H01L21/022 ,  H01L21/0217 ,  H01L21/28176 ,  H01L21/28202 ,  H01L21/28247 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/3185 ,  H01L21/76838 ,  H01L21/76897 ,  H01L29/513 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/792

摘要： Disclosed is a semiconductor device comprising a semiconductor substrate, a gate electrode, a first insulating film formed between the semiconductor substrate and the gate electrode, and a second insulating film formed along a top surface or a side surface of the gate electrode and including a lower silicon nitride film containing nitrogen, silicon and hydrogen and an upper silicon nitride film formed on the lower silicon nitride film and containing nitrogen, silicon and hydrogen, and wherein a composition ratio N/Si of nitrogen (N) to silicon (Si) in the lower silicon nitride film is higher than that in the upper silicon nitride film.

摘要翻译： 公开了一种半导体器件，包括半导体衬底，栅电极，形成在半导体衬底和栅电极之间的第一绝缘膜，以及沿着栅电极的顶表面或侧表面形成的第二绝缘膜， 包含氮，硅和氢的氮化硅膜和形成在下部氮化硅膜上并含有氮，硅和氢的上部氮化硅膜，并且其中氮（N）与硅（Si）的组成比N / Si在 下氮化硅膜比上述氮化硅膜高。

公开(公告)号：US20070215958A1

公开(公告)日：2007-09-20

申请号：US11798593

申请日：2007-05-15

申请人： Masayuki Tanaka ,  Yoshio Ozawa ,  Shigehiko Saida ,  Akira Goda ,  Mitsuhiro Noguchi ,  Yuichiro Mitani ,  Yoshitaka Tsunashima

发明人： Masayuki Tanaka ,  Yoshio Ozawa ,  Shigehiko Saida ,  Akira Goda ,  Mitsuhiro Noguchi ,  Yuichiro Mitani ,  Yoshitaka Tsunashima

IPC分类号： H01L29/94

CPC分类号： H01L21/022 ,  H01L21/0217 ,  H01L21/28176 ,  H01L21/28202 ,  H01L21/28247 ,  H01L21/28518 ,  H01L21/3185 ,  H01L21/76838 ,  H01L21/76897 ,  H01L29/40117 ,  H01L29/513 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/792

摘要： Disclosed is a semiconductor device comprising a semiconductor substrate, a gate electrode, a first insulating film formed between the semiconductor substrate and the gate electrode, and a second insulating film formed along a top surface or a side surface of the gate electrode and including a lower silicon nitride film containing nitrogen, silicon and hydrogen and an upper silicon nitride film formed on the lower silicon nitride film and containing nitrogen, silicon and hydrogen, and wherein a composition ratio N/Si of nitrogen (N) to silicon (Si) in the lower silicon nitride film is higher than that in the upper silicon nitride film.

摘要翻译： 公开了一种半导体器件，包括半导体衬底，栅电极，形成在半导体衬底和栅电极之间的第一绝缘膜，以及沿着栅电极的顶表面或侧表面形成的第二绝缘膜， 包含氮，硅和氢的氮化硅膜和形成在下部氮化硅膜上并含有氮，硅和氢的上部氮化硅膜，并且其中氮（N）与硅（Si）的组成比N / Si在 下氮化硅膜比上述氮化硅膜高。

公开(公告)号：US20060141701A1

公开(公告)日：2006-06-29

申请号：US11359573

申请日：2006-02-23

申请人： Shigehiko Saida ,  Kiyotaka Miyano ,  Takashi Nakao

发明人： Shigehiko Saida ,  Kiyotaka Miyano ,  Takashi Nakao

IPC分类号： H01L21/8242

CPC分类号： H01L27/10861 ,  H01L27/10867

摘要： A semiconductor device having a trench capacitor is disclosed. The trench is formed on the surface of a semiconductor substrate. A first insulating film is formed on the side wall of the trench and a semiconductor film is buried in the trench. The first insulating film and the semiconductor film located in the upper part of the trench are etched and a second insulating film is deposited on the exposed side wall. The semiconductor film and the first insulating film are etched and a plate electrode is formed on the exposed side wall. A capacitor insulating film is formed on the plate electrode and a storage electrode is buried within the trench. The structure provides a semiconductor device having fewer memory cell defects.

摘要翻译： 公开了一种具有沟槽电容器的半导体器件。 沟槽形成在半导体衬底的表面上。 第一绝缘膜形成在沟槽的侧壁上，半导体膜被埋在沟槽中。 蚀刻位于沟槽上部的第一绝缘膜和半导体膜，并在暴露的侧壁上沉积第二绝缘膜。 蚀刻半导体膜和第一绝缘膜，并在暴露的侧壁上形成平板电极。 电容绝缘膜形成在平板电极上，并且存储电极被埋在沟槽内。 该结构提供了具有较少存储单元缺陷的半导体器件。

公开(公告)号：US20050006686A1

公开(公告)日：2005-01-13

申请号：US10770470

申请日：2004-02-04

申请人： Shigehiko Saida ,  Kiyotaka Miyano ,  Takashi Nakao

发明人： Shigehiko Saida ,  Kiyotaka Miyano ,  Takashi Nakao

IPC分类号： H01L27/108 ,  H01L21/8242 ,  H01L29/76

CPC分类号： H01L27/10861 ,  H01L27/10867

摘要： A semiconductor device having a trench capacitor is disclosed. The trench is formed on the surface of a semiconductor substrate. A first insulating film is formed on the side wall of the trench and a semiconductor film is buried in the trench. The first insulating film and the semiconductor film located in the upper part of the trench are etched and a second insulating film is deposited on the exposed side wall. The semiconductor film and the first insulating film are etched and a plate electrode is formed on the exposed side wall. A capacitor insulating film is formed on the plate electrode and a storage electrode is buried within the trench. The structure provides a semiconductor device having fewer memory cell defects.

摘要翻译： 公开了一种具有沟槽电容器的半导体器件。 沟槽形成在半导体衬底的表面上。 第一绝缘膜形成在沟槽的侧壁上，半导体膜被埋在沟槽中。 蚀刻位于沟槽上部的第一绝缘膜和半导体膜，并在暴露的侧壁上沉积第二绝缘膜。 蚀刻半导体膜和第一绝缘膜，并在暴露的侧壁上形成平板电极。 在平板电极上形成电容器绝缘膜，并且将存储电极埋设在沟槽内。 该结构提供了具有较少存储单元缺陷的半导体器件。

公开(公告)号：US07541233B2

公开(公告)日：2009-06-02

申请号：US12007751

申请日：2008-01-15

申请人： Yoshio Ozawa ,  Shigehiko Saida ,  Yuji Takeuchi ,  Masanobu Saito

发明人： Yoshio Ozawa ,  Shigehiko Saida ,  Yuji Takeuchi ,  Masanobu Saito

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825

摘要： A semiconductor device comprises a semiconductor substrate, and a non-volatile memory cell provided on the semiconductor substrate, the non-volatile memory cell comprising a tunnel insulating film having a film thickness periodically and continuously changing in a channel width direction of the non-volatile memory cell, a floating gate electrode provided on the tunnel insulating film, a control gate electrode provided above the floating gate electrode, and an interelectrode insulating film provided between the control gate electrode and the floating gate electrode.

摘要翻译： 半导体器件包括半导体衬底和设置在半导体衬底上的非易失性存储单元，所述非易失性存储单元包括隧道绝缘膜，所述隧道绝缘膜具有在非易失性的沟道宽度方向周期性且连续变化的膜厚度 存储单元，设置在隧道绝缘膜上的浮置栅电极，设置在浮置栅电极上方的控制栅电极，以及设置在控制栅电极和浮栅之间的电极间绝缘膜。

公开(公告)号：US20080119021A1

公开(公告)日：2008-05-22

申请号：US12007751

申请日：2008-01-15

申请人： Yoshio Ozawa ,  Shigehiko Saida ,  Yuji Takeuchi ,  Masanobu Saito

发明人： Yoshio Ozawa ,  Shigehiko Saida ,  Yuji Takeuchi ,  Masanobu Saito

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825

摘要： A semiconductor device comprises a semiconductor substrate, and a non-volatile memory cell provided on the semiconductor substrate, the non-volatile memory cell comprising a tunnel insulating film having a film thickness periodically and continuously changing in a channel width direction of the non-volatile memory cell, a floating gate electrode provided on the tunnel insulating film, a control gate electrode provided above the floating gate electrode, and an interelectrode insulating film provided between the control gate electrode and the floating gate electrode.

摘要翻译： 半导体器件包括半导体衬底和设置在半导体衬底上的非易失性存储单元，所述非易失性存储单元包括隧道绝缘膜，所述隧道绝缘膜具有在非易失性的沟道宽度方向周期性且连续变化的膜厚度 存储单元，设置在隧道绝缘膜上的浮置栅电极，设置在浮置栅电极上方的控制栅电极，以及设置在控制栅电极和浮栅之间的电极间绝缘膜。

公开(公告)号：US5866930A

公开(公告)日：1999-02-02

申请号：US697448

申请日：1996-08-23

申请人： Shigehiko Saida ,  Yoshio Ozawa

发明人： Shigehiko Saida ,  Yoshio Ozawa

IPC分类号： H01L21/28 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/16 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11526 ,  H01L21/28035 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/11546 ,  H01L29/1604 ,  H01L29/42324 ,  H01L27/115

摘要： A semiconductor device comprises a first conducting layer, a first insulating layer formed on the first conducting layer, a second conducting layer formed on the first insulating layer and facing the first conducting layer, wherein, at least part of a peripheral portion of the region of at least one of the first and second conducting layers, in contact with the first insulating layer, includes an amorphous conducting layer made of a semiconductor, and the amorphous conducting layer contains at least one element selected from the group consisting of oxygen, nitrogen, carbon, argon, chlorine, and fluorine and a total concentration of the at least one element falls within the range from 0.1 atomic % to 20 atomic %.

摘要翻译： 半导体器件包括第一导电层，形成在第一导电层上的第一绝缘层，形成在第一绝缘层上并面向第一导电层的第二导电层，其中，至少部分该区域的周边部分 与第一绝缘层接触的第一和第二导电层中的至少一个包括由半导体制成的非晶导体层，并且非晶导体层含有选自氧，氮，碳的至少一种元素 ，氩，氯和氟，并且所述至少一种元素的总浓度在0.1原子％至20原子％的范围内。